M32CSLASH86 datasheet(249/505 Pages) RENESAS

249 / 505 page

Page 226

17. Serial I/O (Special Function)

)

(

17.6 Special Mode 4 (IE Mode)

In IE mode, devices connected with the IEBus can communicate in UART mode.

Table 17.30 lists register settings. Tables 17.31 to 17.33 list pin settings.

Table 17.30 Register Settings in IE Mode

Bit

Function

UiTB

8 to 0

Set transmit data

UiRB

8 to 0

Received data can be read

OER, FER,

Error flags

PER, SUM

UiBRG

7 to 0

Set bit rate

UiMR

SMD2 to SMD0

Set to "1102"

CKDIR

Select the internal clock or external clock

STPS

Set to "0"

PRY

Disabled because the PRYE bit is set to "0"

PRYE

Set to "0"

IOPOL

Select TxD and RxD I/O polarity

UiC0

CLK1, CLK0

Select count source for the UiBRG register

CRS

Disabled because the CRD bit is set to "1"

TXEPT

Transfer register empty flag

CRD

Set to "1"

NCH

Select output format of the TxDi pin

CKPOL

Set to "0"

UFORM

Set to "0"

UiC1

Set to "1" to enable data transmission

Transfer buffer empty flag

Set to "1" te enable data reception

Reception complete flag

UiIRS

Select what causes the UARTi transmit interrupt to be generated

UiRRM, UiLCH,

Set to "0"

SCLKSTPB

UiSMR

3 to 0

Set to "00002"

ABSCS

Select bus conflict detect sampling timing

ACSE

Set to "1" to automatically clear the transmit enable bit

SSS

Select transmit start condition

SCLKDIV

Set to "0"

UiSMR2

7 to 0

Set to "0016"

UiSMR3

7 to 0

Set to "0016"

UiSMR4

7 to 0

Set to "0016"

IFSR

IFSR6, IFSR7

Select how the bus conflict interrupt occurs

i=0 to 4

M32C/86 Datasheet(PDF) 249 Page - Renesas Technology Corp

M32C/86 Datasheet(HTML) 249 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL