M32CSLASH86 datasheet(252/505 Pages) RENESAS

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Page 229

17. Serial I/O (Special Function)

)

(

(1) The ABSCS Bit in the UiSMR Register (Bus conflict and sampling clock selected)

Bus conflict is detected on the rising edge of the transfer clock

when the ABSCS bit is set to "0"

Transfer Clock

Timer Aj

(2) The ACSE Bit in the UiSMR Register (Transmit enable bit is automatically cleared)

IR bit in

BCNilC register

TE bit in

UiC1 register

(3) The SSS bit in the UiSMR Register (Transmit start condition is selected)

TxDi

transmit enable conditons are met

CLKi

TxDi

RxDi

NOTES:

1. Data is transmitted on the falling edge of a signal applied to the RxDi pin when the IOPOL bit is set to "0".

Data is transmitted on the rising edge of a signal applied to the RxDi pin when the IOPOL bit is set to "1".

2. Data transmission condition must be met before the falling edge of the RxDi pin.

When the SSS bit is set to "0", data is transmitted after one transfer clock cycle

if data transmission is enabled.

TxDi

RxDi

Trigger signal is applied to the TAjIN pin

When the ABSCS bit is set to "1", bus conflict is detected when the timer Aj

underflows (in the one-shot timer mode). An interrupt request is generated.

Timer Aj: timer A3 in UART0 or UART3, timer A4 in UART1 or UART4, timer A0 in UART2

Transfer Clock

TxDi

RxDi

Transfer Clock

When the SSS bit is set to "1", data is transmitted on the falling edge of RxDi(1)

(Note 2)

(i=0 to 4)

Figure 17.28 Bit Function Related Bus Conflict Detection

M32C/86 Datasheet(PDF) 252 Page - Renesas Technology Corp