M32CSLASH86 datasheet(305/505 Pages) RENESAS

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22. Intelligent I/O (Waveform Generating Function)

)

(

22.3.1 Single-Phase Waveform Output Mode

Output signal level of the OUTC1j pin becomes high ("H") when the base timer value matches the G1POj

"000016". If the IVL bit in the G1POCRj register is set to "1" ("H" output as default value), an "H" signal

output is provided when waveform output starts. If the INV bit is set to "1" (output inversed), the level of

the waveform output is inversed. See Figure 22.16 for details on single-phase waveform output mode

operation. Table 22.9 lists specifications of single-phase waveform output mode.

Table 22.9 Single-Phase Waveform Output Mode Specifications

Item

Specification

Output Waveform(2)

• Free-running operation

(the RST2 and RST1 bits in the G1BCR1 register are set to "002")

Cycle

"L" width

"H" width

m : setting value of the G1POj register (j=0 to 7), 000016 to FFFF16

• The base timer is cleared to "000016" by matching the base timer with the

G1PO0 register (the RST1 bit is set to "1" and the RST2 bit is set to "0")

Cycle

"L" width

"H" width

m : setting value of the G1POj register (j=1 to 7), 000016 to FFFF16

n : setting value of the G1PO0 register, 000116 to FFFD16

If m

≥ n+2, the output level is fixed to "L"

Waveform Output Start Condition(1) The IFEj bit in the G1FE register is set to "1" (channel j function enabled)

Waveform Output Stop Condition

The IFEj bit is set to "0" (channel j function disabled)

Interrupt Request

The PO1jR bit in the interrupt request register is set to "1" (interrupt

requested) when the base timer value matches the G1POj register setting.

(See Figure 11.14)

OUTC1j Pin

Pulse signal output pin

Selectable Function

• Default value set function: Set starting waveform output level

• Inversed output function:

Waveform output signal is inversed and provided from the OUTC1j pin

NOTES:

1. Set the FSCj bit in the G1FS register to "0" (waveform generating function selected).

2. When the INV bit in the G1POCRj register is set to "1" (output inversed), the "L" width and "H" width are inversed.

fBT1

65536-m

fBT1

n+2

fBT1

n+2-m

fBT1

65536

fBT1

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