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M32C/86 Datasheet(PDF) 309 Page - Renesas Technology Corp |
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M32C/86 Datasheet(HTML) 309 Page - Renesas Technology Corp |
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309 / 505 page ![]() Page 286 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 22. Intelligent I/O (Waveform Generating Function) ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M 22.3.3 Set/Reset Waveform Output (SR Waveform Output) Mode Output signal level of the OUTC1j pin becomes high ("H") when the base timer value matches the G1POj register (j=0, 2, 4, 6) setting. The "H" signal switches to a low-level ("L") signal when the base timer value matches the G1POk register (k=j+1) setting or when the base timer is set to "000016". If the IVL bit in the G1POCRj register is set to "1" ("H" output as default value), an "H" signal output is provided when wave- form output starts. If the INV bit is set to "1" (output inversed), the level of the output waveform is inversed. Table 22.11 lists specifications of SR waveform output mode. Figure 22.18 shows an example of a SR waveform output mode operation. Table 22.11 SR Waveform Output Mode Specifications Item Specification Output Waveform(2) • Free-running operation (the RST2 and RST1 bits in the G1BCR1 register are set to "002") (1) m < n "H" width : "L" width : (2) m ≥ n "H" width : "L" width : m : setting value of the G1POj register (j=0, 2, 4, 6 ) n : setting value of the G1POk register (k=j+1) • The base timer is cleared to "000016" by matching the base timer with the G1PO0 register(1) (the RST1 bit is set to "1" and the RST2 bit is set to "0") (1) m < n < p+2 "H" width : "L" width : (2) m < p+2 ≤ n "H" width : "L" width : (3) If m ≥ p+2, the output level is fixed to "L" m : setting value of the G1POj register (j=2, 4, 6), 000016 to FFFF16 n : setting value of the G1POk register (k=j+1), 000016 to FFFF16 p : setting value of the G1PO0 register, 000116 to FFFD16 NOTES: 1. When the G1PO0 register resets the base timer, the channel 0 and 1 SR waveform generating functions are not available. 2. When the INV bit in the G1POCRj register is set to "1" (output inversed), the "L" width and "H" width are inversed. 3. Waveform from base timer reset until when output level becomes "H". 4. Waveform from when output level becomes "L" until base timer reset. m (3) fBT1 n-m fBT1 + 65536 - n(4) fBT1 65536 - m fBT1 m fBT1 n-m fBT1 m (3) fBT1 + p + 2 - n(4) fBT1 p + 2 - m fBT1 m fBT1 |
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