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M32C/86 Datasheet(PDF) 311 Page - Renesas Technology Corp |
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M32C/86 Datasheet(HTML) 311 Page - Renesas Technology Corp |
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311 / 505 page ![]() Page 288 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 22. Intelligent I/O (Waveform Generating Function) ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M FFFF16 m n n-m fBT1 65536 fBT1 000016 m p+2 n 000016 65536-n+m fBT1 n-m fBT1 p+2-n+m fBT1 p+2 fBT1 (1) Free-Running Operation (The RST2 to RST0 bits in the G1BCR1 register are set to "002") i=0 to 4, 8 to 10; j=0, 2, 4, 6; k=j+1 m : Setting value of the G1POj register, 000016 to FFFF16 n: Setting value of the G1POk register, 000016 to FFFF16 Write "0" by program if setting to "0" Write "0" by program if setting to "0" (2) The Base Timer is Reset when the Base Timer Matches the G1PO0 Register (The RST1 bit is set to "1" and the RST2 bit is set to "0") i=0 to 4, 8 to 10; j=2, 4, 6; k=j+1 m : Setting value of the G1POj register, 000016 to FFFF16 n: Setting value of the G1POk register, 000016 to FFFF16 p: Setting value of the G1PO0 register, 000116 to FFFD16 Write "0" by program if setting to "0" Write "0" by program if setting to "0" Base timer OUTC1j pin PO1jR bit in the IIOiIR register PO1kR bit in the IIOiIR register Base Timer OUTC1j pin(1) OUTC1j pin(2) PO1jR bit in the IIOiIR register PO1kR bit in the IIOiIR register The above applies to the following conditions: • The IVL bit in the G1POCRj register is set to "0" ("L" output as default value) and the INV bit is set to "0" (not inversed). • The UD1 and UD0 bits are set to "002" (counter increment mode). • m<n<p+2 NOTES: 1. Waveform output when the INV bit in the G1POCRj register is set to "0" (not inversed) and the IVL bit in the G1POCRj register is set to "0" (output "L" as default value). 2. Waveform output when the INV bit is set to "0" (not inversed) and the IVL bit is set to "1" ("H" output as default value). "H" "H" "L" "L" "0" "1" "0" "1" "H" "L" "0" "0" "1" "1" The above applies to the following conditions: • The RST2 and RST1 bits in the G1BCR1 register are set to "002" (no base timer reset) and the UD1 and UD0 bits in the G1BCR1 register to "002" (counter increment mode). • m<n Figure 22.18 SR Waveform Output Mode |
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