M32CSLASH86 datasheet(326/505 Pages) RENESAS

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22. Intelligent I/O (Communication Function)

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22.4.2 Clock Asynchronous Serial I/O (UART) Mode (Communication Unit 1)

In clock asynchronous serial I/O (UART) mode, data is transmitted at a desired bit rate and in a desired

transfer data format. Table 22.20 lists specifications of UART mode in the communication unit 1. Table

22.21 lists clock settings. Table 22.22 lists register settings. Tables 22.23 and 22.24 list pin settings.

Figure 22.30 shows an example of transmit operation. Figure 22.31 shows an example of receive opera-

tion.

Table 22.20 UART Mode Specifications (Communication Unit 1)

Item

Specification

Transfer Data Format

• Character bit (transfer data) :

8 bits long

• Start bit :

1 bit long

• Parity bit:

selected from odd, even, or none

• Stop bit :

selected length from 1 bit or 2 bits

Transfer Clock(1)

See Table 22.21

Transmit Start Condition

Set registers associated with the waveform generating function, the G1MR and G1ERC

registers. Then, set as is written below after at least one transfer clock cycle:

• Set the TE bit in the G1CR register to "1" (transmit enable)

• Set the TI bit in the G1CR register to "0" (data written to the G1TB register)

Receive Start Condition

Set registers associated with the waveform generating function, the G1MR and G1ERC

registers. Then, set as is written below after at least one transfer clock cycle:

• Set the RE bit in the G1CR register to "1" (receive enable)

• Detect the start bit

Interrupt Request

• While transmitting, one of the following conditions can be selected to set the

SIO1TR bit to "1" (interrupt requested) (See Figure 11.14.) :

_ The IRS bit in the G1MR register is set to "0" (no data in the G1TB register) and data

is transferred to the transmit register from the G1TB register.

_ The IRS bit is set to "1" (transmission completed) and data transfer from the

transmit register is completed

• While receiving, the following condition can be selected to set the SIO1RR bit is set

to "1":

Data is transferred from the receive register to the G1RB register (data reception

is completed)

Error Detection

• Overrun error(2)

This error occurs, when the next data reception is started and the final stop bit of the

next data is received before reading the G1RB register

• Parity error

While parity is enabled, this error occurs when the number of "1" in parity and char-

acter bits does not match the number of "1" set

• Framing error

This error occurs when the number of the stop bits set is not detected

Selectable Function

• Stop bit length

The length of the stop bit is selected from 1 bit or 2 bits

• LSB first or MSB first

Select either bit 0 or bit 7 to transmit or receive data

NOTES:

1. The transfer clock must be fBT1 divided by six or more.

2. When an overrun error occurs, the G1RB register is indeterminate.

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