M32CSLASH86 datasheet(329/505 Pages) RENESAS

329 / 505 page

Page 306

22. Intelligent I/O (Communication Function)

)

(

22.4.3 HDLC Data Processing Mode (Communication Units 0 and 1)

In HDLC data processing mode, bit stuffing, flag detection, abort detection and CRC calculation are available

for HDLC control. f1, f8 or f2n can be selected as the communication unit 0 transfer clock. f1, f8, f2n or clock,

generated in the channel 0 or 1, can be selected as the communication unit 1 transfer clock. No pin is used.

To convert data, data to be transmitted is written to the GiTB register (i=0,1) and the data conversion result is

restored after data conversion. If any data are in the GiTO register after data conversion, the conversion is

terminated. If no data is in the GiTO register, bit stuffing processing is executed regardless of no data avail-

able in the transmit output buffer. A CRC value is calculated every time one bit is converted. If no data is in the

GiRI register, received data conversion is terminated.

Table 22.25 list specifications of the HDLC data processing mode. Tables 22.26 and 22.27 list clock settings.

Table 22.28 lists register settings.

Table 22.25 HDLC Processing Mode Specifications (Communication Units 0 and 1)

Item

Specification

Input Data Format

8-bit data fixed, bit alignment is optional

Output Data Format

8-bit data fixed

Transfer Clock

See Tables 22.26 and 22.27

I/O Method

• During transmit data processing,

value set in the GiTB register is converted in HDLC data processing mode and

transferred to the GiTO register.

• During received data processing,

value set in the GiRI register is converted in HDLC data processing mode and

transferred to the GiRB register. The value in the GiRI register is also transferred to

the GiTB register (received data register).

Bit Stuffing

During transmit data processing, "0" following five continuous "1" is inserted.

During received data processing, "0" following five continuous "1" is deleted.

Flag Detection

Write the flag data "7E16" to the GiCMPj register (j=0 to 3) to use the special commu-

nication interrupt (the SRTiR bit in the IIO4IR register)

Abort Detection

Write the masked data "0116" to the GiMSKj register

CRC

The CRC1 and CRC0 bits are set to "112" (X16+X12+X5+1).

The CRCV bit is set to "1" (set to "FFFF16").

• During transmit data processing,

CRC calculation result is stored into the GiTCRC register. The TCRCE bit in the

GiETC register is set to "1" (transmit CRC used).

The CRC calculation result is reset when the TE bit in the GiCR register is set to "0"

(transmit disabled).

• During received data processing,

CRC calculation result is stored into the GiRCRC register. The RCRCE bit in the

GiERC register is set to "1" (receive CRC used).

The CRC calculation result is reset by comparing the flag data "7E16" and matching

the result with the value in the GiCMP3 register. The ACRC bit in the GiEMR regis-

M32C/86 Datasheet(PDF) 329 Page - Renesas Technology Corp

M32C/86 Datasheet(HTML) 329 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL