M32CSLASH86 datasheet(331/505 Pages) RENESAS

331 / 505 page

Page 308

22. Intelligent I/O (Communication Function)

)

(

Table 22.28 Register Settings in HDLC Processing Mode (Communication Units 0 and 1)

Bit

Function

G1BCR0

BCK1, BCK0

Select count source

DIV4 to DIV0

Select divide ratio of count source

Select the base timer interrupt

G1BCR1(1)

7 to 0

Set to "0001 00102"

G1POCR0(1)

7 to 0

Set to "0000 00002"

G1POCR1(1)

7 to 0

Set to "0000 00002"

G1PO0(1)

15 to 0

Set bit rate

G1PO1(1)

15 to 0

Set the timing of the rising edge of the transfer clock.

Timing of the falling edge ("H" width of the transfer clock) is fixed.

Setting value of the G1PO1 register

≤ Setting value of the G1PO0 register

G1FS(1)

FSC1, FSC0

Set to "002"

G1FE(1)

IFE1, IFE0

Set to "112"

GiMR

GMD1, GMD0

Set to "112"

CKDIR

Set to "0"

UFORM

Set to "0"

IRS

Select what causes the transmit interrupt to be generated

GiEMR

7 to 0

Set to "1111 01102"

GiCR

Transmit buffer empty flag

TXEPT

Transmit register empty flag

Receive complete flag

Transmit enable bit

Receive enable bit

GiETC

SOF

Set to "0"

TCRCE

Select whether transmit CRC is used or not

ABTE

Set to "0"

TBSF1, TBSF0

Transmit bit stuffing

GiERC

CMP2E to CMP0E Select whether received data is compared or not

CMP3E

Set to "1"

RCRCE

Select whether receive CRC is used or not

RSHTE

Set to "1" to use it in the receiver

RBSF1, RBSF0

Receive bit stuffing

GiIRF

BSERR, ABT

Set to "0"

IRF3 to IRF0

Select what causes an interrupt to be generated

GiCMP0,

7 to 0

Write "FE16" to abort processing

GiCMP1

GiCMP2

7 to 0

Data to be compared

GiCMP3

7 to 0

Write "7E16"

GiMSK0,

7 to 0

Write "0116" to abort processing

GiMSK1

GiTCRC

15 to 0

Transmit CRC calculation result can be read

GiRCRC

15 to 0

Receive CRC calculation result can be read

GiTO

7 to 0

Data, which is output from a transmit data generation circuit, can be read

GiRI

7 to 0

Set data input to a receive data generation circuit

GiRB

7 to 0

Received data is stored

GiTB

7 to 0

For transmission: write data to be transmitted

For reception

: received data for comparison is stored

CCS

CCS1, CCS0

Select the HDLC processing clock

CCS3, CCS2

Select the HDLC processing clock

i=0, 1

NOTES:

1. These register settings are required when the CCS3 and CCS2 bit in the CCS register are set to "002"

(clock output from channel j (j=1 to 3)).

M32C/86 Datasheet(PDF) 331 Page - Renesas Technology Corp

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