M32CSLASH86 datasheet(323/505 Pages) RENESAS

323 / 505 page

Page 300

22. Intelligent I/O (Communication Function)

)

(

Table 22.14 Clock Settings (Communication Unit 1)

Transfer Clock(3)

G1MR Register

CCS Register

CKDIR Bit

CCS2 Bit

CCS3 Bit

fBT1

n+2)

f2n(2)

Input from ISCLK1

n: Setting value of the G1PO0 register, 000116 to FFFD16

NOTES:

1. The transfer clock is generated in phase-delayed waveform output mode of the channel 3 waveform

generating function.

2. The CNT3 to CNT0 bits in the TCSPR register select no division (

n=0) or divide-by-2n (n=1 to 15).

3. The transfer clock must be fBT1 divided by six or more.

Table 22.15 Register Settings in Clock Synchronous Serial I/O Mode (Communication Units 0 and 1)

Bit

Function

Communication Unit 1

Communication Unit 0

CCS

CCS1, CCS0

Setting not required when using the

Select transfer clock

communication unit 1 only

CCS3, CSS2

Select transfer clock

Setting not required when using the

G1BCR0(2)

BCK1, BCK0

Set to "112" (f1)

communication unit 0 only

DIV4 to DIV0

Select divide ratio of count source

Set to "0"

G1BCR1(2)

7 to 0

Set to "0001 00102"

G1POCR0(2)

7 to 0

Set to "0000 01112"

G1POCR1(2)

7 to 0

Set to "0000 01112"

G1POCR3(2)

MOD2 to MOD0

Set to "0102"(1)

IVL

Select default ISCLKi output value(1)

RLD

Set to "0"

INV

Select whether ISCLKi puts in an

inversed signal or not(1)

G1PO0(2)

15 to 0

Set bit rate

= transfer clock

frequency

G1PO3(2)

15 to 0

Set to a value smaller than the G1PO0

G1FS(2)

FSC3,FSC1,FSC0 Set to "0"(1)

G1FE(2)

IFE3,IFE1,IFE0

Set to "1"(1)

GiERC

7 to 0

Set to "0010 00002"

GiMR

GMD1, GMD0

Set to "012"

CKDIR

Select the internal clock or external clock

STPS

Set to "0"

UFORM

Select either LSB first or MSB first

IRS

Select what cause the transmit interrupt to be generated

GiCR

Transmit buffer empty flag

TXEPT

Transmit register empty flag

Receive complete flag

Set to "1" to enable transmission and reception

Set to "1" to enable reception

IPOL

Select ISRxDi input polarity (usually set to "0")

OPOL

Select ISTxDi output polarity (usually set to "0")

GiTB

–

Write data to be transmitted

GiRB

–

Received data and error flag are stored

i = 0 to 1

NOTES:

1. The CKDIR bit in the GiMR register is set to "0" (internal clock).

2. These registers must be set, when f8 or f2n is selected as transfer clock source notwithstanding.

fBT1

2 x (setting value + 2)

(1)

M32C/86 Datasheet(PDF) 323 Page - Renesas Technology Corp

M32C/86 Datasheet(HTML) 323 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL