CY8CTST120
Document Number: 001-46932 Rev. *B
Page 21 of 32
AC Chip Level Specifications
Table 21 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T
A ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C. These are for
design guidance only.
FlashENT
Flash Endurance (total)[10]
1,800,000
–
–
–
Erase/write cycles.
FlashDR
Flash Data Retention
10
–
–
Years
Table 20. DC Programming Specifications (continued)
Table 21. AC Chip Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FIMO245V
Internal Main Oscillator Frequency for 24
MHz (5V)
23.04
24
24.96[11,12]
MHz
Trimmed for 5V operation using
factory trim values.
FIMO243V
Internal Main Oscillator Frequency for 24
MHz (3.3V)
22.08
24
25.92[12,13]
MHz
Trimmed for 3.3V operation using
factory trim values.
FIMOUSB5V Internal Main Oscillator Frequency with USB
(5V)
Frequency locking enabled and USB traffic
present.
23.94
24
24.06[12]
MHz
-10°C
≤ T
A ≤ 85°C
4.35
≤ Vdd ≤ 5.15
FIMOUSB3V Internal Main Oscillator Frequency with USB
(3.3V)
Frequency locking enabled and USB traffic
present.
23.94
24
24.06[12]
MHz
-0°C
≤ T
A ≤ 70°C
3.15
≤ Vdd ≤ 3.45
FCPU1
CPU Frequency (5V Nominal)
0.93
24
24.96[11,12]
MHz
FCPU2
CPU Frequency (3.3V Nominal)
0.93
12
12.96[12,11]
MHz
FBLK5
Digital PSoC Block Frequency (5V Nominal) 0
48
49.92[11,12,13] MHz
Refer to the AC digital block
specifications.
FBLK3
Digital PSoC Block Frequency (3.3V
Nominal)
0
24
25.92[12,14]
MHz
F32K1
Internal Low Speed Oscillator Frequency
15
32
64
kHz
Jitter32k
32 kHz Period Jitter
–
100
ns
Step24M
24 MHz Trim Step Size
–
50
–
kHz
Fout48M
48 MHz Output Frequency
46.08
48.0
49.92[11,13]
MHz
Trimmed. Utilizing factory trim
values.
Jitter24M1 24 MHz Period Jitter (IMO) Peak-to-Peak
–
300
ps
FMAX
Maximum Frequency of signal on row input or
row output.
–
–
12.96
MHz
TRAMP
Supply Ramp Time
0
–
–
μs
Notes
10. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2
blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block
ever sees more than 50,000 cycles).
11. 4.75V < Vdd < 5.25V.
12. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
13. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for
operation at 3.3V.
14. See the individual user module data sheets for information on maximum frequencies for user modules.
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