LPC2921 datasheet(10/81 Pages) PHILIPS

10 / 81 page

LPC2921_2923_2925_0

Preliminary data sheet

Rev. 00.01 — 24 October 2008

10 of 81

NXP Semiconductors

LPC2921/2923/2925

ARM9 microcontroller with CAN and LIN

• Write buffers for the AHB and TCM buses

• Enhanced 16 × 32 multiplier capable of single-cycle MAC operations and 16-bit fixed-

point DSP instructions to accelerate signal-processing algorithms and applications.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. The ARM968E-S is based on the ARMv5TE five-stage pipeline

architecture. Typically, in a three-stage pipeline architecture, while one instruction is being

executed its successor is being decoded and a third instruction is being fetched from

memory. In the five-stage pipeline additional stages are added for memory access and

write-back cycles.

The ARM968E-S processor also employs a unique architectural strategy known as

THUMB, which makes it ideally suited to high-volume applications with memory

restrictions or to applications where code density is an issue.

The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the

ARM968E-S processor has two instruction sets:

• Standard 32-bit ARMv5TE set

• 16-bit THUMB set

The THUMB set's 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM's performance advantage over a

traditional 16-bit controller using 16-bit registers. This is possible because THUMB code

operates on the same 32-bit register set as ARM code.

THUMB code can provide up to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM controller connected to a 16-bit memory system.

The ARM968E-S processor is described in detail in the ARM968E-S data sheet Ref. 2.

6.3 On-chip flash memory system

The LPC2921/2923/2925 includes a 128 kB, 256 kB, or 512 kB flash memory system.

This memory can be used for both code and data storage. Programming of the flash

memory can be accomplished via the flash memory controller or the JTAG.

The flash controller also supports a 16 kB, byte-accessible on-chip EEPROM integrated

on the LPC2921/2923/2925.

6.4 On-chip static RAM

In addition to the two 16 kB TCMs, the LPC2921/2923/2925 includes up two static RAM

memories of 16 kB each for a total of 32 kB (LPC2925 only) or 1 block of 16 kB

(LPC2921/2923). Both may be used for code and/or data storage.

The 8 kB SRAM block for the ETB can be used as static memory for code and data

storage as well. However, DMA access to this memory region is not supported.

LPC2921 Datasheet(PDF) 10 Page - NXP Semiconductors

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