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XC9515 Datasheet(PDF) 13 Page - Torex Semiconductor |
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XC9515 Datasheet(HTML) 13 Page - Torex Semiconductor |
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13 / 21 page ![]() 13/21 XC9515 Series ■NOTES ON USE (Continued) 7. Driving current below the minimum operating voltage may lead malfunction to the UVLO circuit because of the noise. 8. Depending on the PC board condition, the latch function may be released from limit current detection state and the latch time may extend or fail to reach the latch operation. Please locate the input capacitance as close to the IC as possible. 9. Spike noise and ripple voltage arise in a switching regulator as with a DC/DC converter. These are greatly influenced by external component selection, such as the coil inductance, capacitance values, and board layout of external components. Once the design has been completed, verification with actual components should be done. 10. With the DC/DC converter block of the IC, the peak current of the coil is controlled by the current limit circuit. Since the peak current increases when dropout voltage or load current is high, current limit starts operating, and this can lead to instability. When peak current becomes high, please adjust the coil inductance value and fully check the circuit operation. In addition, please calculate the peak current according to the following formula: Peak current: Ipk = (VIN - VOUT) x OnDuty / (2 x L x fosc) + IOUT L: Coil Inductance Value, fOSC: Oscillation Frequency 11. When the load current is light in PWM control, very narrow pulses will be outputted, and there is the possibility that some cycles may be skipped completely. 12. When the difference between VIN and VOUT is small, and the load current is heavy, very wide pulses will be outputted and there is the possibility that some cycles may be skipped completely. 13. If the power input pin voltage is assumed to decrease rapidly (ex. from 6.0V to 0V) at the release of the operation although delay capacitance (Cd) pin is connected, please connect an Shottky barrier diode between the power input (P_VDD1) pin and the delay capacitance (Cd) pin. 14. Please connect a pull-up resistor with 100 to 200kΩ to the output pin of the voltage detector block (VDOUT). 15. The delay time of the voltage detector block in heavy load may extend because of the noise of the DC/DC block. Precipitous and large voltage fluctuation at the power input pin may cause malfunction of the IC. 16. Use of the IC at voltages below the minimum operating voltage may lead the output voltage drop before achieving over current limit. 17. When P_VDD1 and P_VDD2 power supply pins and EN1 and EN2 enable pins are in undefined states, the latch protection circuit may not be reset so that the IC operation does not start correctly. Power supply and enable pins ( EN1,EN2) should be grounded before starting the IC operation. 【 Undefined state conditions for each pin】 P_VDD1=P_VDD2=0.1V ~ 1.2V VEN1=VNE2= 0.4V ~ 1.2V 18. UVLO function works even if when VIN input voltage falls below the UVLO voltage in very short time period like a few ten nanoseconds. ● Instruction on Pattern Layout 1. In order to stabilize VIN's voltage level, we recommend that a by-pass capacitor (CIN1 and CIN2) be connected as close as possible to the P_VDD1・P_VDD2 pins and P_VSS1・P_VSS2 pins. 2. Please mount each external component as close to the IC as possible. 3. Wire external components as close to the IC as possible and use thick, short connecting traces to reduce the circuit impedance. 4. Make sure that the VSS traces are as thick as possible, as variations in the VSS potential caused by high VSS currents at the time of switching may result in instability of the DC/DC converter. |
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