TMS320VC33 datasheet(6/57 Pages) TI

6 / 57 page

TMS320VC33

DIGITAL SIGNAL PROCESSOR

SPRS087E − FEBRUARY 1999 − REVISED JANUARY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

Terminal Functions

TERMINAL

TYPE†

DESCRIPTION

CONDITIONS

WHEN

NAME

QTY

TYPE†

DESCRIPTION

WHEN

SIGNAL IS Z TYPE‡

PRIMARY-BUS INTERFACE

D31 − D0

I/O/Z

32-bit data port

D31 − D0

I/O/Z

Data port bus keepers (See Figure 9)

A23 − A0

O/Z

24-bit address port

R/W

O/Z

Read / write. R/ W is high when a read is performed and low when a write is performed

over the parallel interface.

STRB

O/Z

Strobe. For all external-accesses

PAGE0 −

PAGE3

O/Z

Page strobes. Four decoded page strobes for external access.

RDY

Ready. RDY indicates that the external device is prepared for a transaction

completion.

HOLD

Hold. When HOLD is a logic low, any ongoing transaction is completed. A23 − A0,

D31−D0, STRB, and R / W are placed in the high-impedance state and all

transactions over the primary-bus interface are held until HOLD becomes a logic high

or until the NOHOLD bit of the primary-bus-control register is set.

HOLDA

O/Z

Hold acknowledge. HOLDA is generated in response to a logic-low on HOLD.

HOLDA indicates that A23−A0, D31−D0, STRB, and R / W are in the high-impedance

state and that all transactions over the bus are held. HOLDA is high in response to

a logic-high of HOLD or the NOHOLD bit of the primary-bus-control register is set.

CONTROL SIGNALS

RESET

Reset. When RESET is a logic low, the device is in the reset condition. When RESET

becomes a logic high, execution begins from the location specified by the reset

vector.

EDGEMODE

Edge mode. Enables interrupt edge mode detection.

INT3 − INT0

External interrupts

IACK

O/Z

Interrupt acknowledge. IACK is generated by the IACK instruction. IACK can be used

to indicate when a section of code is being executed.

MCBL / MP

Microcomputer Bootloader / microprocessor mode-select

SHZ

Shutdown high impedance. When active, SHZ places all pins in the high-impedance

state. SHZ can be used for board-level testing or to ensure that no dual-drive

conditions occur. CAUTION: A low on SHZ corrupts the device memory and register

contents. Reset the device with SHZ high to restore it to a known operating condition.

XF1, XF0

I/O/Z

External flags. XF1 and XF0 are used as general-purpose I / Os or to support

interlocked processor instruction.

SERIAL PORT 0 SIGNALS

CLKR0

I/O/Z

Serial port 0 receive clock. CLKR0 is the serial shift clock for the serial port 0 receiver.

CLKX0

I/O/Z

Serial port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0

transmitter.

DR0

I/O/Z

Data-receive. Serial port 0 receives serial data on DR0.

DX0

I/O/Z

Data-transmit output. Serial port 0 transmits serial data on DX0.

FSR0

I/O/Z

Frame-synchronization pulse for receive. The FSR0 pulse initiates the data-receive

process using DR0.

FSX0

I/O/Z

Frame-synchronization pulse for transmit. The FSX0 pulse initiates the data-transmit

process using DX0.

† I = input, O = output, Z = high-impedance state

‡ S = SHZ active, H = HOLD active, R = RESET active

§ Recommended decoupling. Four 0.1 µF for CVDD and eight 0.1 µF for DVDD.

TMS320VC33 Datasheet(PDF) 6 Page - Texas Instruments

TMS320VC33 Datasheet(HTML) 6 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

Datasheet Download

Link URL