MPC2F35 datasheet(11/46 Pages) MEGAWIN

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MPC2F35_USB Data Sheet

0201H

FCPU_SR

CKS

√

At the 6M Hz external crystal, the internal clock source of MPC2F35 is 3M Hz by the default value.

CKS: FCPU clock source select register. 0: FOSC/2 (default), 1:FOSC

Release halt mode enable flag

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0202H

RLH_EN

INT1

INT0

TM0

USB

√

Programmer can select the interrupt sources to release the halt mode through this register.

0: Disable (default), 1: Enable

After setting RLH_EN register, once there is one interrupt to release the halt mode, the programmer can

check the corresponding bit of the IRQ_ST register to know which interrupt source to execute this

release process.

Timer

Timer 0

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00C5H

TM0

√

00C6H

TM0_CTL

STC

RL/S

TKI2

TKI1

TKI0

√

STC: Timer clock disable/enable. 0: Disable timer clock (default), 1: Enable timer clock

RL/S: Auto-reload disable/enable. 0: Enable auto-reload (default), 1: Disable auto-reload

TKI2

TKI1

TKI0

Timer 0 clock source (FTM0CK)

FOSC / 8

FOSC / 16

FOSC / 32

FOSC / 64

FOSC / 128

FOSC / 256

FOSC / 512

FOSC / 1024

When timer 0 is used, it starts to pre-load value to this down-counter by setting the STC bit in the

TM0_CTL SFR and its underflow frequency (FTM0_UV) of timer 0 can be calculated by the following

equation:

FTM0_UV = FTM0CK / (TM0+1),

where FTM0CK is selected by TKI2, TKI1 and TKI0

For example: if FOSC=6M Hz and TKI2=0, TKI1=1, TKI0=0, then FTM0CK= FOSC / 32

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