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MCP2021 Datasheet(PDF) 16 Page - Microchip Technology

Part # MCP2021
Description  LIN Transceiver with Voltage Regulator
PDF  46 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP2021 Datasheet(HTML) 16 Page - Microchip Technology

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MCP2021/2
DS22018E-page 16
© 2009 Microchip Technology Inc.
2.2
DC Specifications
DC Specifications
Electrical Characteristics:
Unless otherwise indicated, all limits are specified for:
VBB = 6.0V to 18.0V
TA = -40°C to +125°C
CLOADREG = 10 µF
Parameter
Sym
Min.
Typ.
Max.
Units
Conditions
Power
VBB Quiescent Operating
Current
IBBQ
115
210
µA
IOUT = 0 mA,
LBUS recessive
—
120
215
µA
VOUT = 3.3V
VBB Transmitter-off
Current
IBBTO
—
90
190
µA
With VREG on, transmitter
off, receiver on, FAULT/
TXE = VIL, CS = VIH
—
95
210
µA
VOUT = 3.3V
VBB Power-down Current
IBBPD
—16
26
µA
With VREG powered-off,
receiver on and transmitter
off, FAULT/TXE = VIH,
TXD = VIH, CS = VIL)
VBB Current with VSS
Floating
IBBNOGND
-1
—
1mA
VBB = 12V, GND to VBB,
VLIN = 0-18V
Microcontroller Interface
High Level Input Voltage
(TXD, FAULT/TXE)
VIH
2.0 or
(0.25VREG
+0.8)
—
VREG
+0.3
V
Low Level Input Voltage
(TXD, FAULT/TXE)
VIL
-0.3
—
0.15 VREG
V
High Level Input Current
(TXD, FAULT/TXE)
IIH
-2.5
—
—
µA
Input voltage = 0.8*VREG
Low Level Input Current
(TXD, FAULT/TXE)
IIL
-10
—
—
µA
Input voltage = 0.2*VREG
Pull-up Current on Input
(TXD)
IPUTXD
-3.0
—
—
µA
~800 k
Ω internal pull-up to
VREG @ VIH = 0.7*VREG
High Level Input Voltage
(CS/LWAKE)
VIH
0.7VREG
—
VBB
V
Through a current-limiting
resistor
Low Level Input Voltage
(CS/LWAKE)
VIL
-0.3
—
0.3VREG
V
High Level Input Current
(CS/LWAKE)
IIH
—
—
7.0
µA
Input voltage = 0.8*VREG
Low Level Input Current
(CS/LWAKE)
IIL
—
—
3.0
µA
Input voltage = 0.2*VREG
Pull-down Current on
Input (CS/LWAKE)
IPDCS
—
—
6.0
µA
~1.3M
Ω internal pull-down
to VSS @ VIH = 3.5V
Note 1:
Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0
Ω, TX = 0.4 VREG, VLBUS = VBB).
2:
For design guidance only, not tested.
3:
Node has to sustain the current that can flow under this condition; bus must be operational under this
condition.



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