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PCIMX515CJM6C Datasheet(PDF) 46 Page - Freescale Semiconductor, Inc |
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PCIMX515CJM6C Datasheet(HTML) 46 Page - Freescale Semiconductor, Inc |
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46 / 184 page  i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 46 Freescale Semiconductor Preliminary—Subject to Change Without Notice Electrical Characteristics Figure 19. WEIM Inputs Timing Diagram Table 40. WEIM Bus Timing Parameters 1 ID Parameter BCD = 0 BCD = 1 BCD = 2 BCD = 3 Min Max Min Max Min Max Min Max WE1 BCLK Cycle time2 t — 2t — 3t — 4t — WE2 BCLK Low Level Width 0.4t — 0.8t — 1.2t — 1.6t — WE3 BCLK High Level Width 0.4t — 0.8t — 1.2t — 1.6t — WE4 Clock rise to address valid3 0.5t-1.25 0.5t+1.75 t-1.25 t+1.75 2t-1.25 2t+1.75 3t-1.25 3t+1.75 WE5 Clock rise to address invalid 0.5t-1.25 0.5t+1.75 t-1.25 t+1.75 2t-1.25 2t+1.75 3t-1.25 3t+1.75 WE6 Clock rise to CSx_B valid 0.5t-1.25 0.5t+1.75 t-1.25 t+1.75 2t-1.25 2t+1.75 3t-1.25 3t+1.75 WE7 Clock rise to CSx_B invalid 0.5t-1.25 0.5t+1.75 t-1.25 t+1.75 2t-1.25 2t+1.75 3t-1.25 3t+1.75 WE8 Clock rise to WE_B Valid 0.5t-1.25 0.5t+1.75 t-1.25 t+1.75 2t-1.25 2t+1.75 3t-1.25 3t+1.75 WE9 Clock rise to WE_B Invalid 0.5t-1.25 0.5t+1.75 t-1.25 t+1.75 2t-1.25 2t+1.75 3t-1.25 3t+1.75 WE10 Clock rise to OE_B Valid 0.5t-1.25 0.5t+1.75 t-1.25 t+1.75 2t-1.25 2t+1.75 3t-1.25 3t+1.75 WE11 Clock rise to OE_B Invalid 0.5t-1.25 0.5t+1.75 t-1.25 t+1.75 2t-1.25 2t+1.75 3t-1.25 3t+1.75 WE12 Clock rise to BEy_B Valid 0.5t-1.25 0.5t+1.75 t-1.25 t+1.75 2t-1.25 2t+1.75 3t-1.25 3t+1.75 WE13 Clock rise to BEy_B Invalid 0.5t-1.25 0.5t+1.75 t-1.25 t+1.75 2t-1.25 2t+1.75 3t-1.25 3t+1.75 WE14 Clock rise to ADV_B Valid 0.5t-1.25 0.5t+1.75 t-1.25 t+1.75 2t-1.25 2t+1.75 3t-1.25 3t+1.75 WE15 Clock rise to ADV_B Invalid 0.5t-1.25 0.5t+1.75 t-1.25 t+1.75 2t-1.25 2t+1.75 3t-1.25 3t+1.75 WE16 Clock rise to Output Data Valid 0.5t-1.25 0.5t+1.75 t-1.25 t+1.75 2t-1.25 2t+1.75 2t-1.25 2t+1.75 WE17 Clock rise to Output Data Invalid 0.5t-1.25 0.5t+1.75 t-1.25 t+1.75 2t-1.25 2t+1.75 2t-1.25 2t+1.75 WE18 Input Data setup time to Clock rise 2— 2 — 2 — 2 — WE19 Input Data hold time from Clock rise 2.5 — 2.5 — 2.5 — 2.5 — Input Data WAIT_B BCLK WE19 WE18 WE21 WE20 |
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