ATmega162 datasheet(92/324 Pages) ATMEL

92 / 324 page

2513K–AVR–07/09

ATmega162/V

Figure 35. Output Compare Unit, Block Diagram

The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM)

modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double

buffering is disabled. The double buffering synchronizes the update of the OCR0 Compare Reg-

ister to either top or bottom of the counting sequence. The synchronization prevents the

occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR0 Register access may seem complex, but this is not case. When the double buffering

is enabled, the CPU has access to the OCR0 Buffer Register, and if double buffering is disabled

the CPU will access the OCR0 directly.

Force Output

Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOC0) bit. Forcing Compare Match will not set the

OCF0 Flag or reload/clear the Timer, but the OC0 pin will be updated as if a real Compare

Match had occurred (the COM01:0 bits settings define whether the OC0 pin is set, cleared or

toggled).

Compare Match

Blocking by TCNT0

Write

All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the

next timer clock cycle, even when the timer is stopped. This feature allows OCR0 to be initialized

to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is

enabled.

OCFn (Int.Req.)

= (8-bit Comparator )

OCRn

OCn

DATA BUS

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMn1:0

bottom

ATmega162 Datasheet(PDF) 92 Page - ATMEL Corporation