ATmega162 datasheet(166/324 Pages) ATMEL

166 / 324 page

166

2513K–AVR–07/09

ATmega162/V

USART

The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a

highly flexible serial communication device. The main features are:

• Full Duplex Operation (Independent Serial Receive and Transmit Registers)

• Asynchronous or Synchronous Operation

• Master or Slave Clocked Synchronous Operation

• High Resolution Baud Rate Generator

• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits

• Odd or Even Parity Generation and Parity Check Supported by Hardware

• Data OverRun Detection

• Framing Error Detection

• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter

• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete

• Multi-processor Communication Mode

• Double Speed Asynchronous Communication Mode

Dual USART

The ATmega162 has two USARTs, USART0 and USART1. The functionality for both USARTs is

described below.

USART0 and USART1 have different I/O Registers as shown in “Register Summary” on page

304. Note that in ATmega161 compatibility mode, the double buffering of the USART Receive

Note also that the shared UBRRHI Register in ATmega161 has been split into two separate reg-

isters, UBRR0H and UBRR1H, in ATmega162.

A simplified block diagram of the USART Transmitter is shown in Figure 75. CPU accessible I/O

Registers and I/O pins are shown in bold.

ATmega162 Datasheet(PDF) 166 Page - ATMEL Corporation