AT89LP428 datasheet(81/149 Pages) ATMEL

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3654A–MICRO–8/09

AT89LP428/828

16.3

More About Mode 0

In Mode 0, the UART is configured as a 2-wire half-duplex synchronous serial interface. Serial

data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmit-

ted/received, with the LSB first. Figure 16-1 on page 83 shows a simplified functional diagram of

the serial port in Mode 0 and associated timing. The baud rate is programmable to 1/2 or 1/4 the

oscillator frequency by setting/clearing the SMOD1 bit. However, changing SMOD1 has an

effect on the relationship between the clock and data as described below. The baud rate can

also be generated by Timer 1 by setting TB8. Table 16-4 lists the baud rate options for Mode 0.

Transmission is initiated by any instruction that uses SBUF as a destination register. The “write

to SBUF” signal also loads a “1” into the 9th position of the transmit shift register and tells the TX

Control Block to begin a transmission. The internal timing is such that one full bit slot may elapse

between “write to SBUF” and activation of SEND.

SEND transfers the output of the shift register to the alternate output function line of P3.0, and

also transfers Shift Clock to the alternate output function line of P3.1. As data bits shift out to the

right, “0”s come in from the left. When the MSB of the data byte is at the output position of the

shift register, the “1” that was initially loaded into the 9th position is just to the left of the MSB,

and all positions to the left of that contain “0”s. This condition flags the TX Control block to do

one last shift, then deactivate SEND and set TI.

Table 16-3.

Commonly Used Baud Rates Generated by Timer 2 (TPS = 0000B)

Baud Rate

OSC (MHz)

Timer 2

CP/RL2

C/T2

TCLK or RCLK

Reload Value

62.5K

FFF4H

19.2K

11.059

FFDCH

9.6K

11.059

FFB8H

4.8K

11.059

FF70H

2.4K

11.059

FEE0H

1.2K

11.059

FDC0H

137.5

11.986

EAB8H

110

F2AFH

110

E55EH

Table 16-4.

Mode 0 Baud Rates

TB8

SMOD1

Baud Rate

SYS/4

SYS/2

(Timer 1 Overflow)/4

(Timer 1 Overflow)/2

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