AT89LP428 datasheet(96/149 Pages) ATMEL

96 / 149 page

3654A–MICRO–8/09

AT89LP428/828

17.4

Serial Clock Timing

The TSCK, CPHA, CPOL and SPR bits in SPCR control the shape and rate of SCK. The two

SPR bits provide four possible bit clock rates when the SPI is in master mode. The TSCK bit

also allows a timer-generated bit rate. In slave mode, the SPI will operate at the rate of the

incoming SCK as long as it does not exceed the maximum bit rate. There are also four possible

combinations of SCK phase and polarity with respect to the serial data. CPHA and CPOL deter-

mine which format is used for transmission. The SPI data transfer formats are shown in Figures

17-3 and 17-4. To prevent glitches on SCK from disrupting the interface, CPHA, CPOL, and

SPR should not be modified while the interface is enabled, and the master device should be

enabled before selecting the slave device(s).

Figure 17-3. SPI Transfer Format with CPHA = 0

Note:

*Not defined but normally MSB of character just received.

Figure 17-4. SPI Transfer Format with CPHA = 1

Note:

*Not defined but normally LSB of previously transmitted character.

MSB

LSB

MSB

LSB

SCK CYCLE #

(FOR REFERENCE)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI

(FROM MASTER)

MISO

(FROM SLAVE)

SS (TO SLAVE)

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