PCF2129AT datasheet(56/68 Pages) NXP

56 / 68 page

PCF2129A_1

Product data sheet

Rev. 01 — 13 January 2010

56 of 68

NXP Semiconductors

PCF2129A

Integrated RTC, TCXO and quartz crystal

13. Dynamic characteristics

13.1 SPI-bus timing characteristics

[1]

No load value; bus will be held up by bus capacitance; use RC time constant with application values.

Table 54.

SPI-bus characteristics

VDD = 1.8 V to 4.2 V; VSS =0V; Tamb = −40 °C to +85 °C, unless otherwise specified. All timing values are valid within the

operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage swing of VSS to VDD (see

Figure 41).

Symbol

Parameter

Conditions

VDD =1.8 V

VDD =4.2 V

Unit

Min

Max

Min

Max

Pin SCL

fclk(SCL)

SCL clock frequency

2.0

6.5

MHz

tSCL

SCL time

800

140

tclk(H)

clock HIGH time

100

tclk(L)

clock LOW time

400

rise time

for SCL signal

100

fall time

for SCL signal

100

Pin CE

tsu(CE_N)

CE_N set-up time

th(CE_N)

CE_N hold time

trec(CE_N)

CE_N recovery time

100

tw(CE_N)

CE_N pulse width

0.99

Pin SDI

tsu

set-up time

set-up time for SDI data

hold time

hold time for SDI data

Pin SDO

td(R)SDO

SDO read delay time

CL = 50 pF

225

tdis(SDO)

SDO disable time

[1]

tt(SDI-SDO)

transition time from SDI to

SDO

to avoid bus conflict

PCF2129AT Datasheet(PDF) 56 Page - NXP Semiconductors

PCF2129AT Datasheet(HTML) 56 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

Datasheet Download

Link URL