PCF2129AT datasheet(66/68 Pages) NXP

66 / 68 page

PCF2129A_1

Product data sheet

Rev. 01 — 13 January 2010

66 of 68

NXP Semiconductors

PCF2129A

Integrated RTC, TCXO and quartz crystal

23. Figures

Fig 1.

Block diagram of PCF2129A . . . . . . . . . . . . . . . . .3

Fig 2.

Pin configuration for PCF2129A (SO20) . . . . . . . .4

Fig 3.

Handling address registers . . . . . . . . . . . . . . . . . .6

Fig 4.

Battery switch-over behavior in standard

mode with bit BIE logic 1 (enabled) . . . . . . . . . . .15

Fig 5.

Battery switch-over behavior in direct switching

mode with bit BIE logic 1 (enabled) . . . . . . . . . . .16

Fig 6.

Battery switch-over circuit, simplified block

diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Fig 7.

Typical driving capability of VBBS: (VBBS - VDD)

with respect to the output load current IBBS . . . . .17

Fig 8.

Battery low detection behavior with bit BLIE

logic 1 (enabled) . . . . . . . . . . . . . . . . . . . . . . . . .18

Fig 9.

Power failure event due to battery discharge:

reset occurs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Fig 10. Dependency between POR and oscillator . . . . . .20

Fig 11. Power-On Reset (POR) system. . . . . . . . . . . . . .20

Fig 12. Power-On Reset Override (PORO) sequence,

valid for both I2C-bus and SPI-bus . . . . . . . . . . .21

Fig 13. Data flow of the time function. . . . . . . . . . . . . . . .25

Fig 14. Access time for read/write operations . . . . . . . . .25

Fig 15. Alarm function block diagram. . . . . . . . . . . . . . . .26

Fig 16. Alarm flag timing diagram . . . . . . . . . . . . . . . . . .28

Fig 17. WD_CD set logic 1: watchdog activates an

interrupt when timed out . . . . . . . . . . . . . . . . . . .31

Fig 18. Timestamp detection with two push-buttons

on one the TS pin (e.g. for tamper detection) . . .33

Fig 19. Interrupt block diagram . . . . . . . . . . . . . . . . . . . .37

Fig 20. INT example for SI and MI when TI_TP is

logic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Fig 21. INT example for SI and MI when TI_TP is

logic 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Fig 22. Example of shortening the INT pulse by

clearing the MSF flag . . . . . . . . . . . . . . . . . . . . . .39

Fig 23. AF timing diagram . . . . . . . . . . . . . . . . . . . . . . . .40

Fig 24. STOP bit functional diagram . . . . . . . . . . . . . . . .43

Fig 25. STOP bit release timing . . . . . . . . . . . . . . . . . . . .43

Fig 26. Interface selection . . . . . . . . . . . . . . . . . . . . . . . .44

Fig 27. SDI, SDO configurations . . . . . . . . . . . . . . . . . . .45

Fig 28. Data transfer overview . . . . . . . . . . . . . . . . . . . . .45

Fig 29. SPI-bus write example . . . . . . . . . . . . . . . . . . . . .46

Fig 30. SPI-bus read example . . . . . . . . . . . . . . . . . . . . .46

Fig 31. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Fig 32. Definition of START and STOP conditions. . . . . .47

Fig 33. System configuration . . . . . . . . . . . . . . . . . . . . . .48

Fig 34. Acknowledgement on the I2C-bus . . . . . . . . . . . .48

Fig 35. Bus protocol, writing to registers . . . . . . . . . . . . .49

Fig 36. Bus protocol, reading from registers . . . . . . . . . .49

Fig 37. Device diode protection diagram of

PCF2129A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Fig 38. IDD as a function of temperature . . . . . . . . . . . . .53

Fig 39. IDD as a function of VDD . . . . . . . . . . . . . . . . . . . .54

Fig 40. Characteristic of frequency with respect to

temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Fig 41. SPI-bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Fig 42. I2C-bus timing diagram; rise and fall times

refer to 30 % and 70 % . . . . . . . . . . . . . . . . . . . . 59

Fig 43. Package outline SOT163-1 (SO20) . . . . . . . . . . 60

PCF2129AT Datasheet(PDF) 66 Page - NXP Semiconductors

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