PCF2127ATSLASH1 datasheet(27/80 Pages) NXP

27 / 80 page

PCF2127A_2

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Product data sheet

Rev. 02 — 7 May 2010

27 of 80

NXP Semiconductors

PCF2127A

Integrated RTC, TCXO and quartz crystal

The setting of the PORO mode requires that POR_OVRD in register Control_1 is set logic

1 and that the signals at the interface pins SDA/CE and SCL are toggled as illustrated in

Figure 16. All timings shown are required minimum.

Once the override mode is entered, the device is immediately released from the reset

state and the set-up operation can commence.

The PORO mode is cleared by writing logic 0 to POR_OVRD. POR_OVRD must be

logic 1 before a re-entry into the override mode is possible. Setting POR_OVRD logic 0

during normal operation has no effect except to prevent accidental entry into the PORO

mode.

Fig 15. Power-On Reset (POR) system

Fig 16. Power-On Reset Override (PORO) sequence, valid for both I2C-bus and SPI-bus

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OSCILLATOR

0 = override inactive

1 = override active

0 = clear override mode

1 = override possible

POR_OVRD

SDA/CE

SCL

RESET

OVERRIDE

CLEAR

osc stopped

0 = stopped, 1 = running

reset

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minimum 2000 ns

minimum 500 ns

8 ms

power up

SCL

reset override

SDA/CE

PCF2127AT/1 Datasheet(PDF) 27 Page - NXP Semiconductors

PCF2127AT/1 Datasheet(HTML) 27 Page - NXP Semiconductors

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