PIC18F44J50 datasheet(6/12 Pages) MICROCHIP

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PIC18F46J50 FAMILY

DS80436C-page 6

 2010 Microchip Technology Inc.

6. Module: Low-Power Modes (Deep Sleep)

Entering Deep Sleep mode takes approximately

2TCY, following the SLEEP instruction. Wake-up

events that occur during this Deep Sleep entry

period may not generate a wake-up event.

Work around

If using the RTCC alarm for Deep Sleep wake-up,

code should only enter Deep Sleep mode when

the RTCC Value registers read synchronization bit

(RTCCFG<4>) is clear.

This will prevent missing an RTCC alarm that

could occur during the period after the SLEEP

instruction, but before the Deep Sleep mode has

not been fully entered.

The revision A4 silicon allows insertion of a single

instruction between setting the Deep Sleep Enable

bit (DSEN, DSCONH<7>) and issuing the SLEEP

instruction (see Example 2). The insertion of a NOP

instruction before the SLEEP instruction eliminates

the 2 TCY window where wake-up events could be

missed.

Before using this work around, users should check

their device’s revision ID bits to verify that they

have the A4 silicon. This can be done at run time

by a table read from address, 3FFFFEh.

On revision A2 silicon devices, the instruction can-

not be inserted between setting the DSEN bit and

executing the SLEEP instruction or the device will

enter conventional Sleep mode, not Deep Sleep.

Even on A4 silicon devices, if the firmware imme-

diately executes SLEEP after setting DSEN, the

device will enter Deep Sleep mode without

benefitting from this work around.

Affected Silicon Revisions

EXAMPLE 2:

DEEP-SLEEP WAKE-UP WORK AROUND

EnterDeepSleep:

bsf

DSCONH, DSEN

; Enter Deep Sleep mode on SLEEP instruction

nop

; Not compatible with A2 silicon

sleep

; Enter Deep Sleep mode

(…)

; Add code here to handle wake up events that may

; have been asserted prior to Deep Sleep entry

goto

EnterDeepSleep

; re-attempt Deep Sleep entry if desired

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