PCM4104IPFBREP datasheet(16/43 Pages) TI

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SYSTEM CLOCK REQUIREMENTS

SCKI

SCKIH

SCKIL

PARAMETER

DESCRIPTION

MIN

MAX

UNITS

System Clock Period

t SCKIH

System Clock High Pulse Time

tSCKIL

System Clock Low Pulse Time

t SCKI

PCM4104-EP

SBAS419 – JUNE 2007

PRODUCT OVERVIEW (continued)

The PCM4104 requires a system clock, applied at the SCKI (pin 14) input. The system clock operates at an

integer multiple of the input sampling frequency, or fS. The multiples supported include 128fS, 192fS, 256fS,

384fS, 512fS, or 768fS. The system clock frequency is dependent upon the sampling mode. Table 1 shows the

required system clock frequencies for common audio sampling frequencies. Figure 4 shows the system clock

timing requirements.

Although the architecture of the PCM4104 is tolerant to phase jitter on the system clock, it is recommended that

the user provide a low jitter clock (100 picoseconds or less) for optimal performance.

Table 1. Sampling Modes and System Clock Frequencies for Common Audio Sampling Rates

SAMPLING

SYSTEM CLOCK FREQUENCY (MHz)

SAMPLING

FREQUENCY,

＝fS

MODE

128fS

192fS

256fS

384fS

512fS

768fS

(kHz)

Single Rate

n/a

8.192

12.288

16.384

24.576

Single Rate

44.1

n/a

11.2896

16.9344

22.5792

33.8688

Single Rate

n/a

12.288

18.432

24.576

36.864

Dual Rate

88.2

n/a

22.5792

33.8688

n/a

Dual Rate

n/a

24.576

36.864

n/a

Quad Rate

176.4

22.5792

33.8688

n/a

Quad Rate

192

24.576

36.864

n/a

Figure 4. System Clock Timing Requirements

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