XIO2001IPNP datasheet(36/131 Pages) TI

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SCL From

Master

SDA Output

By Transmitter

SDA Output

By Receiver

XIO2001

SCPS212D – MAY 2009 – REVISED JANUARY 2010

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Data is transferred serially in 8-bit bytes. During a data transfer operation, the exact number of bytes that

are transmitted is unlimited. However, each byte must be followed by an acknowledge bit to continue the

data transfer operation. An acknowledge (ACK) is indicated by the data byte receiver pulling the SDA

signal low, so that it remains low during the high state of the SCL signal. Figure 3-15 illustrates the

acknowledge protocol.

Figure 3-15. Serial-Bus Protocol Acknowledge

The bridge performs three basic serial-bus operations: single byte reads, single byte writes, and multibyte

reads. The single byte operations occur under software control. The multibyte read operations are

performed by the serial EEPROM initialization circuitry immediately after a PCI Express reset. See

Section 3.10.3, Serial-Bus EEPROM Application, for details on how the bridge automatically loads the

subsystem identification and other register defaults from the serial-bus EEPROM.

Figure 3-16 illustrates a single byte write. The bridge issues a start condition and sends the 7-bit slave

device address and the R/W command bit is equal to 0b. A 0b in the R/W command bit indicates that the

data transfer is a write. The slave device acknowledges if it recognizes the slave address. If no

acknowledgment is received by the bridge, then bit 1 (SB_ERR) is set in the serial-bus control and status

another slave acknowledgment is expected. Then the bridge delivers the data byte MSB first and expects

a final acknowledgment before issuing the stop condition.

Figure 3-16. Serial-Bus Protocol – Byte Write

Figure 3-17 illustrates a single byte read. The bridge issues a start condition and sends the 7-bit slave

device address and the R/W command bit is equal to 0b (write). The slave device acknowledges if it

recognizes the slave address. Next, the EEPROM word address is sent by the bridge, and another slave

acknowledgment is expected. Then, the bridge issues a restart condition followed by the 7-bit slave

address and the R/W command bit is equal to 1b (read). Once again, the slave device responds with an

acknowledge. Next, the slave device sends the 8-bit data byte, MSB first. Since this is a 1-byte read, the

bridge responds with no acknowledge (logic high) indicating the last data byte. Finally, the bridge issues a

stop condition.

Feature/Protocol Descriptions

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XIO2001IPNP Datasheet(PDF) 36 Page - Texas Instruments