XIO2001IPNP datasheet(15/131 Pages) TI

15 / 131 page

XIO2001

www.ti.com

SCPS212D – MAY 2009 – REVISED JANUARY 2010

2.6

Terminal Descriptions

The following tables give a description of the terminals. These terminals are grouped in tables by

functionality. Each table includes the terminal name, terminal number, I/O type, and terminal description.

The following list describes the different input/output cell types that appear in the terminal description

tables:

•

HS DIFF IN = High speed differential input

•

HS DIFF OUT = High speed differential output

•

PCI BUS = PCI bus 3-state bidirectional buffer with 3.3-V or 5.0-V clamp rail.

•

LV CMOS = 3.3-V low voltage CMOS input or output with 3.3-V clamp rail

•

BIAS = Input/output terminals that generate a bias voltage to determine a driver's operating current

•

Feed through = these terminals connect directly to macros within the part and not through an input or

output cell.

•

PWR = Power terminal

•

GND = Ground terminal

Table 2-1. Power Supply Terminals

ZGU

ZAJ

PNP

I/O

EXTERNAL

SIGNAL

DESCRIPTION

BALL #

PIN #

TYPE

PARTS

PCIR

A01, K03

D03, J03

I/O

Resistor

PCI Rail. 5.0-V or 3.3-V PCI bus clamp voltage to set

maximum I/O voltage tolerance of the secondary PCI

bus signals. Connect this terminal to the secondary

PCI bus I/O clamp rail through a 1k

Ω resistor.

VDD_15

G04, K07,

J08, H08,

21, 53, 113

PWR

Bypass

1.5-V digital core power terminals

D07, H10,

J07, G08,

capacitors

G10, F10

N13, K13,

G11, F11

VDDA_15

F13, H13

E12, H12

PWR

Pi filter

1.5-V analog power terminal

VDD_33

E04, H03,

E05, G06,

7, 19, 33, 46,

PWR

Bypass

3.3-V digital I/O power terminal

J04, L08,

H07, G07,

62, 100, 111,

capacitors

K09, D09,

H06, F08,

126

C07, D05,

F07, F06,

J12

J11

VDD_33_AUX

J11

J12

PWR

Bypass

3.3-V auxiliary power terminal Note: This terminal is

capacitors

connected to VSS through a pulldown resistor if no

auxiliary supply is present.

VDDA_33

D13

C12

PWR

Pi filter

3.3-V analog power terminal

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