XIO2001IPNP datasheet(106/131 Pages) TI

106 / 131 page

XIO2001

SCPS212D – MAY 2009 – REVISED JANUARY 2010

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6.5

Serial-Bus Data Register

The serial-bus data register reads and writes data on the serial-bus interface. Write data is loaded into this

from the serial bus, this register contains the data read after bit 5 (REQBUSY) in the serial-bus control and

status register (offset 47h, see Section 6.8) is cleared. This register is an alias for the serial-bus data

(PERST), a GRST, or the internally-generated power-on reset.

Device control memory window register offset:

44h

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

6.6

Serial-Bus Word Address Register

The value written to the serial-bus word address register represents the word address of the byte being

read from or written to on the serial-bus interface. The word address is loaded into this register prior to

writing the serial-bus slave address register that initiates the bus cycle. This register is an alias for the

serial-bus word address register in the PCI header (offset B1h, see Section 4.56). This register is reset by

a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

Device control memory window register offset:

45h

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

6.7

Serial-Bus Slave Address Register

The serial-bus slave address register indicates the address of the device being targeted by the serial-bus

cycle. This register also indicates if the cycle will be a read or a write cycle. Writing to this register initiates

the cycle on the serial interface. This register is an alias for the serial-bus slave address register in the

PCI header (offset B2h, see Section 4.57). See Table 6-4 for a complete description of the register

contents.

Device control memory window register offset:

46h

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

Table 6-4. Serial-Bus Slave Address Register Descriptions

BIT

FIELD NAME

ACCESS

DESCRIPTION

7:1(1)

SLAVE_ADDR

Serial-bus slave address. This 7-bit field is the slave address for a serial-bus read or write

transaction. The default value for this field is 000 0000b.

0 (1)

RW_CMD

Read/write command. This bit determines if the serial-bus cycle is a read or a write cycle.

0 = A single byte write is requested (default)

1 = A single byte read is requested

(1)

These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

106

Memory-Mapped TI Proprietary Register Space

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