13 / 20 page

Preliminary
11-129
RF2968
Rev A13 010912
11
In a read operation, the baseband sends the device address, READ bit (R/W = 1), and register address to the RF2968
followed by a “turn-around” bit which lasts half a clock cycle. This turn-around allows the RF2968 to drive its requested
data, via BDDATA, on the rising edges of BDCLK. Following the transfer of the last data bit (D[0]), the baseband drives
BnDEN high and resumes control of BDDATA on the falling edge of the first BDCLK pulse after BnDEN is driven high.
SeeFigure3.
Register Definition
The register address field allows up to 32 registers for various functions. The RF2968 implements only register
addresses 3-7 and 30-31.
Register 3 - IF Register 1 (Read-Only)
Bit Number
Bit Name
Comments
7 - 15
N/A
Not Assigned
0 -6
RSSI[6:0]
The RSSI value indicates the average power measured during the first 10
µs
after a packet has been detected. The baseband reads this register to obtain
the current received signal strength indicator measurement. The RSSI value
may range from 0dBm to -127dBm in 1dB increments. (All 0’s indicates
0dBm; all 1’s indicates -127dBm.) The RSSI circuitry is designed to operate
from -20dBm to -80dBm with an accuracy of 4dB at -60dBm.
Example: RSSI[6:0]= [110101] indicates -53dBm.
BDCLK
BnDEN
Slave Driving BDDATA
Master Driving BDDATA
...
...
D15
A6
A5
A3
A2
A1
A0
A7
A4
D1
D2
D0
A6
A7
BDDATA
don't
care
turn-around
turn-around
R/W = read = 1
D14
Floating
Floating
Figure 3. DBus Read Programming Diagram