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Preliminary
11-125
RF2968
Rev A13 010912
11
Detailed Functional Block Diagram
Pin Out
31
29
28
27
26
25
32
30
LO
VCO
Phase Detector/
Charge Pump
Prescaler
16/17
Synthesizer
Address 7
x2
TX
DATA
SYNC
BT = 0.5
4MHz
ICO
LOOP
FILTER
/4
1MHz
Phase
Detector /
Charge
Pump
/4
Filter
APPF
LO
Σ
Chip
Control
BDATA1
10 MHz
BPKTCTL
BXTLEN
500 kHz
23 BnPWR
24 PLLGND
22 BDCLK
Address 30
Address 31
Address 3
25-Bit Latch
16-Bit Shift
Register
(Read Only)
25-Bit Shift
Register
(Write Only)
21 BDDATA
DBus
25
5
25
20 BnDEN
7
LPO
6
VCC4
5
VCC3
8
DVDDH
4
RXIN
3
TXOUT
2
VCC2
1
VCC1
Σ
APPF
LO
1MHz IF
Transmitter
Clock / Data
Recovery
Receiver
Address 4
Address 5
Address 6
16
16
16
/2
500 kHz
1MHz
/6
/5
10 MHz
60 MHz
/60
Div R
Phase Detector/
Charge Pump
Div R
Ref. Osc.
19 OSC I
18 OSC O
17 BRCLK
LPF/
Equalizer
9
10
11
12
13
14
15
16
12 MHz
FSK Demodulator
TX DATA
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
8
7
6
5
4
3
2
1
PLL GND
BnPWR
BDCLK
BDDATA
BnDEN
OSC I
OSC O
BRCLK
DVDDH
LPO
VCC4
VCC3
RX IN
TX OUT
VCC2
VCC1