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VSC060

Data Sheet

Revision 4.1

January 2008

3.2.27 22h: Port Bypass Control 2 (PBC2)

The following table shows the bit assignments for the Port Bypass Control 2 register. This register

functions the same as the Port Bypass Control 0 register except it affects the P3.5 and P3.4 pins.

PBC2

Address:

22h

Reset Value:

00XX_XX1Xb

Bit

Bit Label

Access

Description

PBCEN

R/W

Port Bypass Control Enable

When this bit is set, P3.5 and P3.4 are automatically configured as an FB

output pin and an SD input pin. Configurations for these I/O pins that may have

been previously enabled through other control registers are overridden, except

for the bypass select function (bits 6 and 5 of the appropriate bit control

registers).

When this bit is reset, the remaining bits in this register have no effect on the

operation of P3.5 and P3.4.

SDIEN

R/W

Signal Detected Interrupt Enable

When this bit is set, the SD input generates an interrupt if a transition occurs

on the pin. If a transition occurs, the INT# pin asserts and a binary value equal

to the address of this register appears in the BCIS register.

When this bit is reset, transitions on the signal detected input do not generate

an interrupt condition.

5:2

RES

Reserved.

R/W

Force Bypass

This bit controls the P3.5 I/O pin, which is configured as a totem pole output by

setting the PBCEN bit.

When this bit is set, the force bypass input of a PBC/CRU/SDU function is not

enabled and the port bypass circuit is in Normal mode.

When this bit is reset, the force bypass function of a PBC/CRU/SDU function is

enabled and the port bypass circuit is in Bypass mode.

This register bit is automatically cleared when the synchronized and filtered

P3.4 input is LOW, resulting in a maximum latency of 400 ns from detection of

the loss of a high-speed signal to the de-assertion of the P3.5 output.

Note: Because all I/O pins on the device power up as inputs with weak internal

pull-up resistors, it is possible to define the default state of the force bypass

function by using an external pull-down resistor. The default state of the I/O

can be determined by reading this register, because the read value of the

the default state is determined, write the default value to the FB bit of this

are enabled correctly. Additional writes to this register can enable or disable

the force bypass functions at any time as long as the SD input remains HIGH.

R/W

Signal Detected

When the PBCEN bit is set, this bit becomes a read-only indication of the P3.4

I/O pin, which is connected to the signal detected output of a PBC/CRU/SDU

function.

If this bit is set, the signal detect unit detects a high-speed signal.

If this bit is reset, the signal detect unit does not detect a high-speed signal.

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