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AS8650

Datasheet - Detailed Descr i p ti on

7.14.3 Time-out Watchdog Behavior

Whenever the AS8650 operates in Standby mode, active watchdog operates in Time-out watchdog mode. The watchdog has to be triggered

interface. If the microcontroller fails to trigger the watchdog within trigger range then the system reset is generated on RESET pin and watchdog

enters into Start-up watchdog mode. The time-out watchdog function is illustrated in Figure 13.

Figure 13. Time-out Watchdog Triggering

7.15 Interrupt Generation

The pin INTN is an interrupt output. The INTN is forced LOW if one bit in the Interrupt register is set. The Interrupt register bits are cleared when

the microcontroller clears the corresponding interrupt source register. The Interrupt register will also be cleared during a system reset (RESET

LOW). As there are microcontrollers with level sensitive or edge sensitive interrupt port, pin INTN will be HIGH for at least TINTN after any of the

interrupt source register is cleared. The Interrupt source register is cleared through write operation by overwriting 1 in to respective set bits

position. Without further interrupts within TINTN pin INTN stays HIGH, otherwise it will revert to LOW again.

The Interrupt register indicates the cause of an interrupt event. There are two levels of interrupt registers. First level register indicates the source

region of interrupt and the second level register indicates the exact source of interrupt. With this structured interrupt, the microcontroller can trace

source of interrupt by two read operations instead of polling for source of interrupt and also interrupts can be prioritized by microcontroller. The

interrupt register structure is given in Figure 14. The register is cleared through digital interface write operation and upon any reset event. The

hardware ensures no interrupt event is lost in case there is a new interrupt forced while reading the register.

TRIGGER WINDOW

NON-TRIGGER WINDOW

Trigger

restarts

period

50%

100%

Last

Trigger

Point

Earliest

Trigger

Point

Latest

Trigger

Point

TRIGGER WINDOW

NON-TRIGGER WINDOW

50%

100%

Earliest

Trigger

Point

Latest

Trigger

Point

Trigger restarts period

( with new period if desired)

New Period

SPI

TRIGGER

SPI

TRIGGER

Unwanted Trigger

(RESET generated,

watchdog enter

Start-up mode)