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AS8650

Datasheet - Application In form atio n

Figure 24. I2C Auto-increment Write Operation

8.2.2 I2C Read Operation

After the START condition, microcontroller has to send, in the first byte, the 7-bit slave address and 0 into the R/W bit as shown in Figure 25. The

microcontroller has to send the address of the register to be written in the second byte. The first 3 MSB bits are reserved and remaining 5 bits are

used as address bits. The data is sent starting from MSB to LSB. After receiving the acknowledgement on the 9th clock pulse, microcontroller

has to send on the SDA line repeated START or STOP, as shown in Figure 25. If microcontroller sends STOP then microcontroller has to send

START again. If microcontroller sends repeated START then there is no need to generate START again. The microcontroller again has to send

the 7-bit slave address and writes 1 into the R/W bit (8th bit). Now AS8650 sends data of the corresponding addressed register in the next eight

clock cycles. In case of single read, microcontroller does not acknowledge on the 9th clock pulse and generates START or STOP condition after

the ninth clock pulse. If it is an auto increment read operation, microcontroller acknowledges on the 9th clock pulse and AS8650 sends data from

the consecutive address locations, see Figure 25. If microcontroller continuously reads then address pointer rolls back to the starting register

address after reaching the last register address. In the data phase MSB is sent first and LSB is sent last. After each data byte, microcontroller

has to send the acknowledgement. The microcontroller can terminate the auto read operation by not generating acknowledgement for the last

byte that was sent by the AS8650 and generates STOP or repeated START condition after the 9th clock pulse.

Figure 25. I2C Read Operation

12

8

9

SCLK

MSB

SDA

Master

transmitter

34

56

7

12

8

9

34

56

7

LSB

12

8

9

34

56

7

A

AA

acknowledge

From slave

acknowledge

From slave

acknowledge

From slave

data to register

S

or

P

data to register + n

R/W

Slave address

S

register address

A0

A1

A2

A3

A4

12

8

9

SCLK

MSB

SDA

34

56

7

12

8

9

34

56

7

LSB

A

A

acknowledge

from slave

acknowledge

from slave

register address

S

or

P

W

Slave address

12

8

9

SCLK

MSB

SDA

34

56

7

12

8

9

34

56

7

LSB

A

A

acknowledge

from slave

acknowledge

from master

Data byte

R

Slave address

0

1

S

S

S

or

P

A0

A1

A2

A3

A4