DS3170_11 datasheet(4/230 Pages) MAXIM

4 / 230 page

DS3170 DS3/E3 Single-Chip Transceiver

4 of 230

10.11 BERT .................................................................................................................................................. 108

10.11.1 General Description ...................................................................................................................... 108

10.11.2 Features ....................................................................................................................................... 108

10.11.3 Configuration and Monitoring ........................................................................................................ 108

10.11.4 Receive Pattern Detection............................................................................................................. 109

10.11.5 Transmit Pattern Generation ......................................................................................................... 111

10.12 LIU – LINE INTERFACE UNIT .................................................................................................................... 112

10.12.1 General Description ...................................................................................................................... 112

10.12.2 Features ....................................................................................................................................... 112

10.12.3 Detailed Description ...................................................................................................................... 112

10.12.4 Transmitter ................................................................................................................................... 113

10.12.5 Receiver ....................................................................................................................................... 114

OVERALL REGISTER MAP

117

119

12.1 REGISTERS BIT MAPS ............................................................................................................................ 119

12.1.1 Global Register Bit Map ................................................................................................................ 119

12.1.2 HDLC Register Bit Map................................................................................................................. 121

12.1.3 T3 Register Bit Map ...................................................................................................................... 123

12.1.4 E3 G.751 Register Bit Map............................................................................................................ 124

12.1.5 E3 G.832 Register Bit Map............................................................................................................ 125

12.2 GLOBAL REGISTERS............................................................................................................................... 126

12.2.1 Register Bit Descriptions ............................................................................................................... 126

12.3 PORT REGISTER .................................................................................................................................... 133

12.3.1 Register Bit Descriptions ............................................................................................................... 133

12.4 BERT .................................................................................................................................................. 144

12.4.1 BERT Register Map ...................................................................................................................... 144

12.4.2 BERT Register Bit Descriptions..................................................................................................... 144

12.5 B3ZS/HDB3 LINE ENCODER/DECODER ................................................................................................... 151

12.5.1 Transmit Side Line Encoder/Decoder Register Map ...................................................................... 151

12.5.2 Receive Side Line Encoder/Decoder Register Map ....................................................................... 152

12.6 HDLC .................................................................................................................................................. 156

12.6.1 HDLC Transmit Side Register Map................................................................................................ 156

12.6.2 HDLC Receive Side Register Map ................................................................................................ 159

12.7 FEAC CONTROLLER .............................................................................................................................. 163

12.7.1 FEAC Transmit Side Register Map................................................................................................ 163

12.7.2 FEAC Receive Side Register Map................................................................................................. 165

12.8 TRAIL TRACE ......................................................................................................................................... 168

12.8.1 Trail Trace Transmit Side .............................................................................................................. 168

12.8.2 Trail Trace Receive Side Register Map ......................................................................................... 169

12.9 DS3/E3 FRAMER ................................................................................................................................... 174

12.9.1 Transmit DS3................................................................................................................................ 174

12.9.2 Receive DS3 Register Map ........................................................................................................... 176

12.9.3 Transmit G.751 E3........................................................................................................................ 183

12.9.4 Receive G.751 E3 Register Map ................................................................................................... 186

12.9.5 Transmit G.832 E3 Register Map .................................................................................................. 191

12.9.6 Receive G.832 E3 Register Map ................................................................................................... 194

JTAG INFORMATION

202

13.1 JTAG DESCRIPTION............................................................................................................................... 202

13.2 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION .......................................................................... 203

13.3 JTAG INSTRUCTION REGISTER AND INSTRUCTIONS ................................................................................... 205

13.4 JTAG ID CODES ................................................................................................................................... 206

13.5 JTAG FUNCTIONAL TIMING ..................................................................................................................... 207

13.6 IO PINS ................................................................................................................................................ 207

PIN CONFIGURATIONS

208

DC ELECTRICAL CHARACTERISTICS

211

AC TIMING CHARACTERISTICS

213

DS3170 Datasheet(PDF) 4 Page - Maxim Integrated Products

DS3170 Datasheet(HTML) 4 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL