DS3170_11 datasheet(6/230 Pages) MAXIM

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DS3170 DS3/E3 Single-Chip Transceiver

6 of 230

LIST OF FIGURES

Figure 2-1. LIU External Connections for the DS3/E3 Port of DS3170 .................................................................. 10

Figure 2-2. Block Diagram ................................................................................................................................... 11

Figure 3-1. DS3/E3 Line Card .............................................................................................................................. 12

Figure 7-1. DS3/E3 Framed LIU Mode ................................................................................................................. 19

Figure 7-2. DS3/E3 Unframed LIU Mode.............................................................................................................. 20

Figure 7-3. DS3/E3 Framed POS/NEG Mode....................................................................................................... 21

Figure 7-4. DS3/E3 Unframed POS/NEG Mode ................................................................................................... 22

Figure 7-5. DS3/E3 Framed UNI Mode................................................................................................................. 23

Figure 7-6. DS3/E3 Unframed UNI Mode ............................................................................................................. 24

Figure 8-1. Tx Line IO B3ZS Functional Timing Diagram...................................................................................... 37

Figure 8-2. Tx Line IO HDB3 Functional Timing Diagram ..................................................................................... 38

Figure 8-3. Rx Line IO B3ZS Functional Timing Diagram...................................................................................... 38

Figure 8-4. Rx Line IO HDB3 Functional Timing Diagram ..................................................................................... 39

Figure 8-5. Tx Line IO UNI Functional Timing Diagram......................................................................................... 39

Figure 8-6. Rx Line IO UNI Functional Timing Diagram ........................................................................................ 40

Figure 8-7. DS3 Framing Receive Overhead Port Timing ..................................................................................... 40

Figure 8-8. E3 G.751 Framing Receive Overhead Port Timing ............................................................................. 40

Figure 8-9. E3 G.832 Framing Receive Overhead Port Timing ............................................................................. 40

Figure 8-10. DS3 Framing Transmit Overhead Port Timing .................................................................................. 41

Figure 8-11. E3 G.751 Framing Transmit Overhead Port Timing .......................................................................... 41

Figure 8-12. E3 G.832 Framing Transmit Overhead Port Timing .......................................................................... 41

Figure 8-13. DS3 Framed Mode Transmit Serial Interface Pin Timing................................................................... 42

Figure 8-14. E3 G.751 Framed Mode Transmit Serial Interface Pin Timing........................................................... 42

Figure 8-15. E3 G.832 Framed Mode Transmit Serial Interface Pin Timing........................................................... 42

Figure 8-16. DS3 Framed Mode Receive Serial Interface Pin Timing.................................................................... 43

Figure 8-17. E3 G.751 Framed Mode Receive Serial Interface Pin Timing............................................................ 43

Figure 8-18. E3 G.832 Framed Mode Receive Serial Interface Pin Timing............................................................ 43

Figure 8-19. SPI Serial Port Access For Read Mode, SPI_CPOL=0, SPI_CPHA = 0 ............................................ 44

Figure 8-20. SPI Serial Port Access For Read Mode, SPI_CPOL = 1, SPI_CPHA = 0 .......................................... 44

Figure 8-21. SPI Serial Port Access For Read Mode, SPI_CPOL = 0, SPI_CPHA = 1 .......................................... 44

Figure 8-22. SPI Serial Port Access For Read Mode, SPI_CPOL = 1, SPI_CPHA = 1 .......................................... 44

Figure 8-23. SPI Serial Port Access For Write Mode, SPI_CPOL = 0, SPI_CPHA = 0........................................... 45

Figure 8-24. SPI Serial Port Access For Write Mode, SPI_CPOL = 1, SPI_CPHA = 0........................................... 45

Figure 8-25. SPI Serial Port Access For Write Mode, SPI_CPOL = 0, SPI_CPHA = 1........................................... 45

Figure 8-26. SPI Serial Port Access For Write Mode, SPI_CPOL = 1, SPI_CPHA = 1........................................... 45

Figure 8-27. 16-Bit Mode Write ............................................................................................................................ 46

Figure 8-28. 16-Bit Mode Read ............................................................................................................................ 46

Figure 8-29. 8-Bit Mode Write .............................................................................................................................. 47

Figure 8-30. 8-Bit Mode Read .............................................................................................................................. 47

Figure 8-31. 16-Bit Mode without Byte Swap........................................................................................................ 48

Figure 8-32. 16-Bit Mode with Byte Swap............................................................................................................. 48

Figure 8-33. Clear Status Latched Register on Read............................................................................................ 49

Figure 8-34. Clear Status Latched Register on Write............................................................................................ 49

Figure 8-35.

RDY Signal Functional Timing Write ................................................................................................. 50

Figure 8-36.

RDY Signal Functional Timing Read................................................................................................. 50

Figure 10-1. Interrupt Structure ............................................................................................................................ 55

Figure 10-2. Internal Tx Clock .............................................................................................................................. 58

Figure 10-3. Internal Rx Clock.............................................................................................................................. 59

Figure 10-4. Example IO Pin Clock Muxing .......................................................................................................... 63

Figure 10-5. Reset Sources ................................................................................................................................. 64

Figure 10-6. 8KREF Logic.................................................................................................................................... 67

Figure 10-7. Performance Monitor Update Logic .................................................................................................. 70

Figure 10-8. Transmit Error Insert Logic ............................................................................................................... 71

Figure 10-9. Loopback Modes.............................................................................................................................. 72

Figure 10-10. ALB Mux ........................................................................................................................................ 72

Figure 10-11. AIS Signal Flow.............................................................................................................................. 74

Figure 10-12. Framer Detailed Block Diagram...................................................................................................... 79

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