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ICS95V857 Datasheet(PDF) 1 Page - Integrated Device Technology |
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ICS95V857 Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 13 page  Integrated Circuit Systems, Inc. ICS95V857 0674U—01/27/09 Block Diagram 2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz) Pin Configuration 48-Pin TSSOP/TVSOP Recommended Application: • DDR Memory Modules / Zero Delay Board Fan Out • Provides complete DDR registered DIMM solution with ICSSSTVF16857, ICSSSTVF16859 or ICSSSTV32852 Product Description/Features: • Low skew, low jitter PLL clock driver • 1 to 10 differential clock distribution (SSTL_2) • Feedback pins for input to output synchronization • PD# for power management • Spread Spectrum-tolerant inputs • Auto PD when input signal removed Specifications: • Meets PC3200 Class A+ specification for DDR-I 400 support • Covers all DDRI speed grades Switching Characteristics: • CYCLE - CYCLE jitter: <50ps • OUTPUT - OUTPUT skew: <40ps • Period jitter: ±30ps S T U P N IS T U P T U O e t a t S L L P D D V A# D PT N I _ K L CC N I _ K L CT K L CC K L CT T U O _ B FC T U O _ B F D N GH L H L H L H f f o / d e s s a p y B D N GH H L H L H L f f o / d e s s a p y B V 5 . 2 ) m o n ( LL H Z Z Z Z f f o V 5 . 2 ) m o n ( LH LZ Z Z Z f f o V 5 . 2 ) m o n ( HL HL H L H n o V 5 . 2 ) m o n ( HH L H L H L n o V 5 . 2 ) m o n ( X) z H M 0 2 < ) 1 ( ZZ Z Z f f o Functionality PLL FB_INT FB_INC CLK_INC CLK_INT PD# Control Logic FB_OUTT FB_OUTC CLKT0 CLKT1 CLKT2 CLKT3 CLKT4 CLKT5 CLKT6 CLKT7 CLKT8 CLKT9 CLKC0 CLKC1 CLKC2 CLKC3 CLKC4 CLKC5 CLKC6 CLKC7 CLKC8 CLKC9 6.10 mm Body, 0.50 mm Pitch = TSSOP 4.40 mm Body, 0.40 mm Pitch = TVSOP GND CLKC0 CLKT0 VDD CLKT1 CLKC1 GND GND CLKC2 CLKT2 VDD VDD CLK_INT CLK_INC VDD AVDD AGND GND CLKC3 CLKT3 VDD CLKT4 CLKC4 GND GND CLKC5 CLKT5 VDD CLKT6 CLKC6 GND GND CLKC7 CLKT7 VDD PD# FB_INT FB_INC VDD FB_OUTC FB_OUTT GND CLKC8 CLKT8 VDD CLKT9 CLKC9 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 |
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