ADA4896-2/ADA4897-1

Rev. 0 | Page 22 of 28

LOW NOISE GAIN SELECTABLE AMPLIFIER

+5V

2

1

8

3

150Ω

–5V

4

ADA4896-2

+5V

6

7

8

5

–5V

4

ADA4896-2

D1

D2

S1B

S1A

S2B

S3B

D3

S2A

V1

V2

150Ω

450Ω

USING S3B IS OPTIONAL

Figure 50. Using the ADA4896-2 and the ADG633 to Construct a Low Noise Gain Selectable Amplifier to Drive a Low Resistive Load

A gain selectable amplifier makes processing a wide range of

input signals possible. The traditional gain selectable amplifier

involves switches in the feedback loops connecting to the

inverting input. In this case the switch resistance degrades the

noise performance of the amplifier, as well as adding significant

capacitance on the inverting input node. The noise and capaci-

tance issue can be especially bothersome when working with

low noise amplifiers. Also, the switch resistances contribute to

nonlinear gain error, which is undesirable.

Figure 50 presents an innovative switching technique used in

the gain selectable amplifier such that the 1 nV/Hz noise per-

formance of the ADA4896-2 is preserved, while the nonlinear

gain error is much reduced. With this technique, one can also

choose switches with minimal capacitance, which optimizes the

bandwidth of the circuit. In this circuit, the switches are

implemented with the ADG633 and they are configured such

that either S1A and S2A are on, or S1B and S2B are on. In this

example, when the S1A and S2A switches are on, the first stage

amplifier gain is +4. When the S1B and S2B switches are on, the

first stage amplifier gain is +2. The first set of switches of the

ADG633 is put in the output side of the feedback loop and the

second set of switches is used to sample at a point (V1 and V2)

where switch resistances and nonlinear resistances do not matter.

This way, the gain error can be reduced while preserving the

noise performance of the ADA4896-2/ADA4897-1.

11.0

11.5

12.0

12.5

13.0

13.5

14.0

–0.40

–0.35

–0.30

–0.25

–0.20

–0.15

–0.10

–0.05

0

0.05

0

0.5

1.0

1.5

2.0

INPUT VOLTAGE (V)

It should be noted that the input bias current of the output

buffer can cause problems with the impedance of the S2A and

S2B sampling switches. Both sampling switches are not only

nonlinear with voltage but with temperature as well. If this is an

issue, place the unused switch of the ADG633 in the feedback

path of the output buffer, as shown in Figure 50, to balance the

bias currents.

The following derivation shows that sampling at V1 yields the

resistance. V2 can be derived with the same method.

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

+

+

×

=

G1

S1

F1

IN

01

R

R

R

V

V

1

(1)

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

+

+

+

×

=

S1

G1

F1

G1

F1

01

1

R

R

R

R

R

V

V

(2)

Substituting (1) into (2), the following derivation is obtained

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

+

×

=

G1

F1

IN

1

R

R

V

V

1

(3)

Figure 51 compares the gain errors when the output signal is

Equation 3. Figure 52 shows the normalized frequency response

–30

–27

–24

–21

–18

–15

–12

–9

–6

–3

0

3

6

FREQUENCY (Hz)

G = +2

G = +4

100k

1M

10M

100M

500M