AD8021 datasheet(26/28 Pages) AD

26 / 28 page

ADA4896-2/ADA4897-1

Rev. 0 | Page 26 of 28

COMPLIANT TO JEDEC STANDARDS MO-178-AB

10°

4°

0°

SEATING

PLANE

1.90

BSC

0.95 BSC

0.60

BSC

3.00

2.90

2.80

3.00

2.80

2.60

1.70

1.60

1.50

1.30

1.15

0.90

0.15 MAX

0.05 MIN

1.45 MAX

0.95 MIN

0.20 MAX

0.08 MIN

0.50 MAX

0.30 MIN

0.55

0.45

0.35

PIN 1

INDICATOR

Figure 57. 6-Lead Small Outline Transistor Package [SOT-23]

(RJ-6)

Dimensions shown in millimeters

2.44

2.34

2.24

TOP VIEW

0.30

0.25

0.20

BOTTOM VIEW

PIN 1 INDEX

AREA

SEATING

PLANE

0.80

0.75

0.70

1.70

1.60

1.50

0.203 REF

0.05 MAX

0.02 NOM

0.50 BSC

EXPOSED

PAD

3.10

3.00 SQ

2.90

PIN 1

INDICATOR

(R 0.15)

FORPROPERCONNECTIONOF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.50

0.40

0.30

COMPLIANT

TO JEDEC STANDARDS MO-229-WEED

Figure 58. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3 mm Body, Very Very Thin, Dual Lead

(CP-8-11)

Dimensions shown in millimeters

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