ADP1046ACPZ-R7 datasheet(80/96 Pages) AD

80 / 96 page

ADP1046

Data Sheet

Rev. 0 | Page 80 of 96

Table 112. Register 0x70—Dead Time Configuration

Bits

Bit Name

R/W

Description

[7:6]

Averaging period

R/W

These bits specify the averaging period for the CS1 current used to set the adaptive dead time. It is

recommended that the averaging time be set to a value much greater than any transient condition.

Bit 7

Bit 6

Averaging Period

2.5 ms

1.2 ms

600 μs

Reserved

[5:3]

Update rate

R/W

The ADT algorithm adjusts the dead time in steps of 5 ns. These bits are used to program the

number of PWM switching cycles between each step. The number is calculated as 2N + 1 where

N is the 3-bit value specified by these bits. If N = 6 (110), each PWM edge is adjusted by 5 ns every

26 + 1 = 65 switching cycles.

[2:0]

Multiplier

R/W

These bits specify the programming step for Register 0x69 to Register 0x6F, Bits[6:4] and Bits[2:0].

Bit 2

Bit 1

Bit 0

Multiplier

SOFT START FILTER PROGRAMMING REGISTERS

Table 113. Register 0x71—Soft Start Digital Filter LF Gain Setting

Bits

Bit Name

R/W

Description

[7:0]

LF gain setting

R/W

This register determines the low frequency gain of the loop response. Programmable over a 20 dB

range. Each LSB corresponds to a 0.3 dB increase. See Figure 57.

Table 114. Register 0x72—Soft Start Digital Filter Zero Setting

Bits

Bit Name

R/W

Description

[7:0]

Zero setting

R/W

This register determines the position of the final zero. See Figure 57.

Table 115. Register 0x73—Soft Start Digital Filter Pole Setting

Bits

Bit Name

R/W

Description

[7:0]

Pole location

R/W

This register determines the position of the final pole. See Figure 57.

Table 116. Register 0x74—Soft Start Digital Filter HF Gain Setting

Bits

Bit Name

R/W

Description

[7:0]

HF gain setting

R/W

This register determines the high frequency gain of the loop response. Programmable over a 20 dB

range. Each LSB corresponds to a 0.3 dB increase. See Figure 57.

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