AR4100 datasheet(22/29 Pages) FREESCALE

22 / 29 page

MKG-16487 Ver. 5.0

Qualcomm Atheros, Inc.

MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION

AR4100 System in Package 802.11n– General Availability Data Sheet

Pin Assignments and Descriptions

Table 5-3

Signal-to-Pin Relationships and Descriptions

Signal Name

Type

Reset

State

I/O Pad Supply

Domain

Description

Digital Control

HMODE0

VDDIO

WiFi host mode select, see design guide for

configuration details, floating input must be

tied high or low.

HMODE1

VDDIO

WiFi host mode select, see design guide for

configuration details, floating input must be

tied high or low.

CHIP_PWD_L

T11

I, PD

Low

HOST_POWER WLAN Power Down

Power down

WLAN awake

Host Interface (SPI Mode)

SPI_MOSI

I/O

HOST_POWER SPI data Input

SPI_CLK

HOST_POWER SPI clock must be driven.

SPI_MISO

I/O

HOST_POWER SPI data output

SPI_INT

I/O

HOST_POWER SPI interrupt

SPI_CS

I/O

HOST_POWER SPI chip select

Master SPI Flash Interface

SPIM_CLK

I/O

VDDIO

Master SPI clock for SPI flash interface

SPIM_CS_N

I/O

High

VDDIO

Master SPI chip select for SPI flash interface

SPIM_MISO

I/O

High

VDDIO

Master SPI data input for SPI flash interface

SPIM_MOSI

I/O

VDDIO

Master SPI data output for SPI flash interface

RF Port

WIFI_RF

A_I/O

N/A

RF antenna port

System Test

DEBUG_

UART_RXD

T10

I/O

Low

VDDIO

Reconfigured after software download as

debugging UART RXD

DEBUG_

UART_TXD

High

VDDIO

Reconfigured after software download as

debugging UART TXD

TMS

I, PU

High

VDDIO

WiFi JTAG TMS

Used with debugging only

TCK

I, PU

High

VDDIO

WiFi JTAG TCK

Used with debugging only

TDI

I, PU

High

VDDIO

WiFi JTAG TDI

Used with debugging only

AR4100 Datasheet(PDF) 22 Page - Freescale Semiconductor, Inc

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