AR4100 datasheet(16/29 Pages) FREESCALE

16 / 29 page

MKG-16487 Ver. 5.0

Qualcomm Atheros, Inc.

MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION

AR4100 System in Package 802.11n– General Availability Data Sheet

Electrical Characteristics

Figure 4-1 and Figure 4-2 show the recommended power up/down and reset sequences for the

AR4100 using external 3.3 V and 1.8 V supplies.

Where:



VBAT = VBATTERY_42



I/O = VDDIO, HOST_POWER

Figure 4-1

Power Up/Power Down Timing

Figure 4-2

Reset and Power Cycle Timing

Table 4-5

Reset and Power Cycle Timing

Variable

Description

Min (

μsec) Max (μsec)

Time between VBAT, VDD33 and I/O supplies becoming valid and 1.8 V

supply becoming valid1

0—

Time between the 1.8 V becoming valid and the CHIP_PWD_L deassertion

500

Time between the CHIP_PWD_L assertion and the 1.8 VG supply becoming

invalid

0—

Time between the 1.8 V supply becoming invalid and VBAT, VDD33 and I/O

supplies becoming invalid

N/A2

—

Length of the CHIP_PWDP_L pulse

—

“Supply becoming valid” denotes that the voltage level has reached 90%

No strict requirements. This parameter can also be negative.

AR4100 Datasheet(PDF) 16 Page - Freescale Semiconductor, Inc