CY2DP818

1:8 Clock Fanout Buffer

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

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408-943-2600

Document Number: 38-07061 Rev. *D

Revised August 20, 2012

1:8 Clock Fanout Buffer

Features

Description

The Cypress CY2DP818 fanout buffer features a single LVDS or

a single ended LVTTL compatible input and eight LVPECL output

pairs.

Designed

for

data-communications

clock

management

applications, the large fanout from a single input reduces loading

on the input clock.

The CY2DP818 is ideal for both level translations from single

ended to LVPECL and/or for the distribution of LVPECL based

clock signals.

The Cypress CY2DP818 has configurable input functions. The

input is user configurable via the InConfig pin for single ended or

differential input.

Logic Block Diagram

INPUT

(LVPECL / LVDS / LVTTL)

OUTPUT

(LVPECL)

Q1A

Q1B

Q2A

Q2B

Q3A

Q3B

Q4A

Q4B

Q5A

Q5B

Q6A

Q6B

Q7A

Q7B

Q8A

Q8B

INPUT A

INPUT B

InConfig