TNETEL1200 datasheet(10/20 Pages) TI1

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TNETEL1200

EtherLoop

™ MODEM

SPHS003D – FEBRUARY 1999 – REVISED JUNE 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Table 1. Processor Interface Signal List

TERMINAL NAME

I/O†

SIGNAL

UPDAT15–UPDAT0

I/O

Microprocessor data bus

UPADDR7–UPADDR0

Microprocessor address bus

UPRWN

Microprocessor read/write enable

UPCSN

Microprocessor chip select (active low)

UPOEN

Microprocessor output enable (active low)

† I = input, O = output

Table 2. Operating Conditions (I/O Terminals)

MICROPROCESSOR

TERMINAL NAME

I/O†

HYSTERESIS

5-V

TOLERANT

3.6-V

FAILSAFE

UPDAT15–UPDAT0

I/O

UPADDR7–UPADDR0

UPRWN

UPCSN

† I = input, O = output

SYSTEM

TERMINAL

NAME

TYPE‡

HYSTERESIS

5-V

TOLERANT

3.6-V

FAILSAFE

XTAL

RESET

‡ I = input

SERIAL LOOP COMMUNICATIONS

TERMINAL

NAME

I/O†

HYSTERESIS

5-V

TOLERANT

3.6-V

FAILSAFE

TXRDY

TXCLK

TXON

TXD

RXRDY

RXCLK

RXON

RXD

† I = input, O = output

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