STW82103B datasheet(33/67 Pages) STMICROELECTRONICS

Part #	STW82103B

Description	RF down converter with embedded integer-N synthesizer

PDF	67 Pages

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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33 / 67 page

STW82103B

I2C bus interface

Doc ID 018517 Rev 2

33/67

I2C bus interface

The I2C bus interface is selected by hardware connection of the pin 25 (DBUS_SEL) to 0 V.

Data transmission from a microprocessor to the STW82103B takes place through the 2

wires (SDA and SCL) I2C-bus interface. The STW82103B is always a slave device.

The I2C-bus protocol defines any device that sends data on to the bus as a transmitter and

any device that reads the data as receiver. The device that controls the data transfer is

known as the master and the others as slaves. The master always initiates the transfer and

provides the serial clock for synchronization.

The STW82103B I2C bus supports Fast Mode operation (clock frequency up to 1 MHz).

9.1

I2C general features

9.1.1

Data validity

Data changes on the SDA line must only occur when the SCL is LOW. SDA transitions while

the clock is HIGH identify START or STOP conditions.

Figure 14.

Data validity waveform

SDA

SCL

Data line stable

Change

data valid

data allowed

STW82103B Datasheet(PDF) 33 Page - STMicroelectronics