STW82103B datasheet(35/67 Pages) STMICROELECTRONICS

35 / 67 page

STW82103B

I2C bus interface

Doc ID 018517 Rev 2

35/67

9.1.4

Device addressing

To start the communication between the Master and the STW82103B, the master must

initiate with a START condition. Following this, the master sends onto the SDA line 8 bits

(MSB first) corresponding to the device select address and read or write mode.

The first 7 MSBs are the device address identifier, corresponding to the I2C-Bus definition.

For the STW82103B the address is set as ’1101A2A1A0’, 3-bits programmable. The 8th bit

(LSB) is the read or write operation bit (the RW bit is set to 1 in read mode and to 0 in write

mode).

After a START condition the STW82103B identifies the device address on the bus and, if

matched, it acknowledge the identification on SDA bus during the 9th clock pulse.

9.1.5

Single-byte write mode

Following a START condition the master sends a device select code with the RW bit set to 0.

The STW82103B gives an acknowledge and waits for the internal sub-address (1 byte). This

byte provides access to any of the internal registers.

After reception of the internal byte sub-address the STW82103B again responds with an

acknowledge. A single-byte write to sub-address 0x00 would affect DATA_OUT[47:40], a

single-byte write with sub-address 0x04 would affect DATA_OUT[15:8] and so on.

9.1.6

Multi-byte write mode

The multi-byte write mode can start from any internal address. The master sends the data

bytes and each one is acknowledged. The master terminates the transfer by generating a

STOP condition.

The sub-address determines the starting byte. For example, a multi-byte write with sub-

address 0x01 and 4 DATA_IN bytes affects 4 bytes starting at address 0x01 (registers at

addresses 0x01, 0x02, 0x03 and 0x04 are modified).

9.1.7

Current byte address read

In the current byte address read mode, following a START condition, the master sends the

device address with the RW bit set to 1 (No sub-address is needed as there is only 1 byte

read register). The STW82103B acknowledges this and outputs the data byte. The master

does not acknowledge the received byte, but terminates the transfer with a STOP condition.

1101A2A1A0

0ack

sub-address

byte

ack

DATA IN

ack

1101A2A1A0

0ack

sub-address

byte

ack

DATA IN

ack

DATA

ack

1101A2A1A0

ack

DATA OUT

No ack

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