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SPEAR300 Datasheet(PDF) 77 Page - STMicroelectronics |
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SPEAR300 Datasheet(HTML) 77 Page - STMicroelectronics |
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77 / 83 page ![]() SPEAr300 Timing requirements Doc ID 16324 Rev 2 77/83 Figure 43. SPI master mode external timing (clock phase = 0) 6.7.2 SPI master mode timings (clock phase = 1) Table 47. Timing requirements for SPI master mode (clock phase = 1) No. Parameters Min Max Unit 4 tsu(DIV- CLKL) Setup time, MISO (input) valid before SSP_CLK (output) falling edge Clock polarity = 0 -0.411 -0.342 ns 5 tsu(DIV- CLKH) Setup time, MISO (input) valid before SSP_CLK (output) rising edge Clock polarity = 1 -0.411 -0.342 ns 6 th(CLKL- DIV) Hold time, MISO (input) valid after SSP_CLK (output) falling edge Clock polarity = 0 0.912 1.720 ns 7 th(CLKH- DIV) Hold time, MISO (input) valid after SSP_CLK (output) rising edge Clock polarity = 1 0.912 1.720 ns Table 48. Switching characteristics over recommended operating conditions for SPI master mode (clock phase = 1 ) No. Parameters Min Max Unit 8 td(CLKH- DOV) Delay time, SSP_CLK (output) rising edge to MOSI (output) transition Clock Polarity = 0 -3.138 2.175 ns 9 td(CLKL- DOV) Delay time, SSP_CLK (output) falling edge to MOSI (output) transition Clock Polarity = 1 -3.138 2.175 ns |
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