SC2308ASTRT datasheet(13/17 Pages) SEMTECH

13 / 17 page

SC2308A

Applications Information (Continued)

The power stage also has a right half plane (RHP) zero at:

(9)

The ESR zero frequency is:

OUT

(0)

where R

C is the ESR of the output capacitor.

3 and C4 form a zero at:

()

With the assumption that C

4>>C6 , R3 and C6 also form a

pole p

3 at frequency:

(2)

There is also a low-frequency integrator pole p

formed

by C

4 and the equivalent output resistance of the trans-

conductance amplifier. The corresponding bode plots are

shown in Figure 8.

Bode Magnitude Plots of the Power Stage, the

Compensator, and the Overall Loop Gain

Figure 8.

Power-Stage

Compensator

Loop Gain

fz1

fp3

fp2

fz2

fz3

fp3,4

Gain (dB)

Crossover Frequency, fC

The poles p

, p2 and the RHP zero z2 all increase phase shift

in the loop response. For stable operation, the overall loop

gain should cross 0dB with -20dB/decade slope. Due to

the presence of the RHP zero, it is suggested that the 0dB

crossover frequency should not be more than

z .

A simple two-pole, single-zero compensator network is

adequate. The loop is compensated with R

3, C4 and C6 from

the COMP pin to ground. The compensating zero z

pro-

vides phase boost beyond p

2. In general, the converter will

be more stable if the filter pole p

2 and the RHP zero z2 are

widely separated. The RHP zero moves to low frequency

when either the duty cycle D or the output current I

OUT

increases. It is beneficial to use small inductors and larger

output capacitors, especially when stepping up from low

IN to high VOUT. An optional second pole can be placed at

the power stage ESR zero to attentuate any high-frequency

noise.

Thermal Shutdown

Thermal shutdown turns off the power switch and the

control circuit as the junction temperature exceeds 60°C.

Switching resumes when the junction temperature falls

by 2°C.

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