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ADV7129 Datasheet(PDF) 13 Page - Analog Devices |
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ADV7129 Datasheet(HTML) 13 Page - Analog Devices |
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13 / 20 page ![]() ADV7129 –13– REV. 0 DIGITAL-TO-ANALOG CONVERTERS (DACS) AND VIDEO OUTPUTS The ADV7129 contains three high speed video DACs. The DAC outputs are represented as the three primary analog color signals IOR (red video), IOG (green video) and IOB (blue video). DACs and Analog Outputs The part contains three matched 8-bit digital-to-analog converters. The DACs are designed using an advanced, high speed, seg- mented architecture. The bit currents corresponding to each digital input are routed to either IOR, IOG, IOB (bit = “1”) or IOR , IOG, IOB (bit = “0”). Normally IOR, IOG, & IOB are connected to GND. ZO = 50Ω (CABLE) ZL = 50Ω (MONITOR) IOR, IOG, IOB DACs ZS = 50Ω (SOURCE TERMINATION) Figure 10. DAC Output Termination (Doubly Terminated 50 Ω Load) The analog video outputs are high impedance current sources. Each of the these three RGB current outputs are specified to di- rectly drive a 25 Ω load (doubly-terminated 50 Ω). Reference Input and RSET An external 1.235 V voltage reference is preferred to set up the analog outputs of the ADV7129. The reference voltage is con- nected to the VREF input. In the absence of an external refer- ence, the on-chip voltage reference is internally connected to the VREF pin. The internal reference will set up the DAC cur- rents, although with slightly less accuracy. A resistor RSET is connected between the RSET (RRSET, RGSET, RBSET) input of the part and ground. An RSET value of 280 Ω corresponds to the generation of two times RS-343A video lev- els into a doubly-terminated 50 Ω load. Figure 11 illustrates the resulting video waveform and the Video Output Truth Table il- lustrates the corresponding control input stimuli. On the ADV7129 SYNC can be encoded on any of the analog signals, however in practice, SYNC is generally encoded on either the IOG output or on all of the video outputs. Any combination of RSET, DAC termination resistors and programming of SYNC and pedestal are possible provided that the maximum DAC current of 60 mA and the DAC output compliance specifications are adhered to. The following tables show the current levels for different values of RSET resistors and RLOAD termination. 7.5 IRE 92.5 IRE 40 IRE SYNC LEVEL BLANK LEVEL BLACK LEVEL WHITE LEVEL Figure 11. Composite Video Waveform SYNC Decoded; Pedestal = 7.5 IRE |
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