TRCV012G5 and TRCV012G7

Preliminary Data Sheet

Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer

August 2000

2

Lucent Technologies Inc.

Table of Contents

Contents

Page

Features .................................................................................................................................................................... 1

Applications ............................................................................................................................................................... 1

Description................................................................................................................................................................. 1

Pin Information .......................................................................................................................................................... 4

Functional Overview ................................................................................................................................................ 10

Limiting Amplifier ..................................................................................................................................................... 10

Limiting Amplifier Operation.................................................................................................................................. 10

Clock and Data Recovery (CDR)............................................................................................................................. 11

Clock Recovery Operation .................................................................................................................................... 11

Clock Recovery PLL Loop Filter ........................................................................................................................... 11

CDR Acquisition Time...........................................................................................................................................11

CDR Generated Jitter ...........................................................................................................................................11

CDR Input Jitter Tolerance ................................................................................................................................... 12

CDR Jitter Transfer ............................................................................................................................................... 12

Clock Recovery Jitter Tolerance and Jitter Transfer Specifications...................................................................... 13

Data Path Configuration Option (ENDATAN) ....................................................................................................... 14

High-Speed Serial Clock and Data Output Enables (ENCK2G5N, END2G5N).................................................... 14

High-Speed Serial Data Output Mute (MUTE2G5N) ............................................................................................ 14

Data and CDR Configuration Options (REFSELN, INLOSN, MUTEDMXN)......................................................... 14

Decision Circuit—Adjustable Sampling Time (ASTREF, AST[4:0])......................................................................... 15

Loss of Signal Detection.......................................................................................................................................... 16

Digital Loss of Signal (LOSDN)............................................................................................................................. 16

Analog Loss of Signal (LOSAN, PRG_LOSA) ......................................................................................................16

Demultiplexer Operation.......................................................................................................................................... 17

Parity Generation (PARITYP/N)............................................................................................................................ 17

Demultiplexer Powerdown (PDDMXN) ................................................................................................................. 17

Demultiplexer Data Mute (MUTEDMXN) .............................................................................................................. 17

CK155P/N Low-Speed Output Mute (MUTE155N)...............................................................................................17

CML Output Structure (Used on Pins D2G5P/N, CK2G5P/N)................................................................................. 18

Choosing the Value of the External CML Reference Resistors (RREF1, RREF2) ............................................... 18

Absolute Maximum Ratings.....................................................................................................................................19

Handling Precautions .............................................................................................................................................. 19

Operating Conditions............................................................................................................................................... 19

Electrical Characteristics ......................................................................................................................................... 20

Limiting Amplifier Specifications ........................................................................................................................... 20

Optional Reference Frequency (REFCLKP/N) Specifications .............................................................................. 20

LVPECL, CMOS, CML Input and Output Pins ......................................................................................................21

Timing Characteristics ............................................................................................................................................. 23

Output Timing ....................................................................................................................................................... 23

Outline Diagram....................................................................................................................................................... 25

128-Pin QFP ......................................................................................................................................................... 25

Board Installation Recommendations ...................................................................................................................26

Thermal Considerations (MBIC 025 BiCMOS and MBIC 025 SiGe BiCMOS) ..................................................... 26

Ordering Information................................................................................................................................................ 27

DS00-234HSPL Replaces DS00-154HSPL to Incorporate the Following Updates................................................. 27