LM3263 datasheet(6/39 Pages) TI

6 / 39 page

LM3263

SNVS837 – JUNE 2013

www.ti.com

SYSTEM CHARACTERISTICS

The following spec table entries are specified by design and verifications providing the component values in the Typical

Application Circuit are used (L = 1.5 µH, DCR = 120 m

Ω, TOKO DFE201610MT-1R5N, CIN = 10 µF, 6.3V, 0402, Samsung

CL05A106MP5NUN, COUT = 10 µF + 4.7 µF + 3 x 1.0 µF; 10V, 0402, Samsung CL05A106MP5NUN, CL05A475MPNRN;

6.3V, 0201, TDK, C0603X5R0J105M). These parameters are not verified by production testing. Min and Max values are

specified over the ambient temperature range TA = -30°C to 90°C. Typical values are specified at VBATT = 3.8V (= PVIN =

SVDD = PACB), VIO = 1.8V, SMPS_CFG = 20h, and TA =25°C unless otherwise stated.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Turn-on time (time for output to reach

VBATT = 4.2V, VSET[7:0] =00h to

TON

95% of 3.4V value from the end of the

µs

E3h, VSET = 3.4V, IOUT ≤ 1mA

SCLK pulse)

Time for VOUT to rise from 0.09V to 3.4V

VBATT = 3.8V, RLOAD = 68Ω

(3.07V, 90% of delta VOUT from the end of VSET[7:0] = 06h to E3h

SCLK pulse)

SMPS_CFG[5] = 0b/1b

Time for VOUT to fall from 3.4V to 0.09V

VBATT = 3.8V, RLOAD = 68Ω

(0.42V, 10% of delta VOUT from the end of VSET[7:0] = E3h to 06h

SCLK pulse)

SMPS_CFG[5] = 0b/1b

Time for VOUT to rise from 0.8V to 3.3V

VBATT = 3.8V, RLOAD = 20Ω

(3.05V, 90% of delta VOUT from the end of

7.4

VSET[7:0] =36h to DCh

SCLK pulse)

Time for VOUT to fall from 3.3V to 0.8V

VBATT = 3.8V, RLOAD = 20Ω

(1.05V, 10% of delta VOUT from the end of

6.8

VSET[7:0] = DCh to 36h

SCLK pulse)

TRESPONSE

µs

Time for VOUT to rise from 1.4V to 3.4V

VBATT = 3.8V, RLOAD = 6.8Ω

(3.2V, 90% of delta VOUT from the end of

VSET[7:0] = 5Eh to E3h

SCLK pulse)

Time for VOUT to fall from 3.4V to 1.4V

VBATT = 3.8V, RLOAD = 6.8Ω

(1.6V, 10% of delta VOUT from the end of

VSET[7:0] = E3h to 5Eh

SCLK pulse)

Time for VOUT to rise from 1.8V to 2.8V

VBATT = 3.8V, RLOAD = 2.2Ω

(2.7V, 90% of delta VOUT from the end of

VSET[7:0] = 78h to BBh

SCLK pulse)

SMPS_CFG[5] = 0b

Time for VOUT to fall from 2.8V to 1.8V

VBATT = 3.8V, RLOAD = 2.2Ω

(1.9V, 10% of delta VOUT from the end of

VSET[7:0] = BBh to 78h

SCLK pulse)

SMPS_CFG[5] = 0b

Time for VSET to rise from 0.09V to PVIN VBATT = 3.6V, IOUT ≤ 1mA,

TBypass

µs

after BYPASS transition (90%)

VSET[7:0] = 06h to FFh

VSET[7:0] = FAh, Max value at VBATT

Rtot-drop

Total dropout resistance in bypass mode

Ω

= 3.1V, Inductor DCR

≤ 151 mΩ

IOUT

Maximum load current in PWM mode

Switcher + ACB

2.5

Maximum output transient pull-up current

IOUT, PU

3.0

limit

Switcher + ACB(1)

PWM maximum output transient pull-

IOUT, PD, PWM

−3.0

down current limit

Maximum output load current in PFM

IOUT, MAX_PFM

VBATT = 3.8V, VSET = 3.2V

mode

VBATT = 3.9V

(2), Monotonic in nature;

−3.0

+3.0

Linearity in control range of VSET = 0.4V

Linearity

VSET[7:0] = 1Bh to F0h,

to 3.6V

−50

+50

SMPS_CFG[5] = 0b

(1)

Current limit is built-in, fixed, and not adjustable.

(2)

Linearity limits are ±3% or ±50 mV whichever is larger.

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